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1. 发明授权

US06400639B1 Wordline decoder system and method 失效
标题翻译：字线解码器系统和方法
公开(公告)号：US06400639B1
公开(公告)日：2002-06-04
申请号：US09712628
申请日：2000-11-14
申请人： Brian L. Ji , Toshiaki Kirihata , Dmitry G. Netis
发明人： Brian L. Ji , Toshiaki Kirihata , Dmitry G. Netis
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/08
摘要： A memory decoder system is disclosed. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.
摘要翻译：公开了一种存储器解码器系统。在本发明的示例性实施例中，系统包括排列成行和列的存储器单元阵列，其中多个字线驱动器对应于矩阵中的每一行。一组字线驱动器 - 解码器块每个包含多个字线驱动器的子集，其中每个字线驱动器 - 解码器块由行控制块分隔。行控制块包括用于字线驱动器的控制电路。对于任何给定的字线驱动器 - 解码器块，其中包含的第一组字线驱动器由位于给定字线驱动器 - 解码器块的一侧上的行控制块控制，而其中包含的第二组字线驱动器由行控制块位于给定字线驱动器 - 解码器块的相对侧。

2. 发明授权

US06185135B2 Robust wordline activation delay monitor using a plurality of sample wordlines 有权
标题翻译：使用多个样本字线的稳健的字线激活延迟监视器
公开(公告)号：US06185135B2
公开(公告)日：2001-02-06
申请号：US09225340
申请日：1999-01-05
申请人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
发明人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C700
CPC分类号： G11C5/063
摘要： A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.
摘要翻译：公开了一种字线激活延迟监视电路，其中至少一个采样字线和采样字线冗余位于存储器的相同数据存储阵列区域内，并且采样字线选择器被耦合以激活采样字线或采样字线冗余处于非易失性输入状态。字线选择器电路可以包括行解码器电路或字线驱动器电路中的一个或两个，其具有与用于激活数据存储阵列区域内的字线的行解码器电路和字线驱动器电路基本相同的结构和位置。

3. 发明授权

US6115310A Wordline activation delay monitor using sample wordline located in data-storing array 有权
标题翻译：字线激活延迟监视器使用位于数据存储阵列中的示例字线
公开(公告)号：US6115310A
公开(公告)日：2000-09-05
申请号：US225343
申请日：1999-01-05
申请人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
发明人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C8/08 , G11C8/14 , G11C8/18 , G11C11/408 , G11C11/4091 , G11C7/02
CPC分类号： G11C8/18 , G11C11/408 , G11C11/4091 , G11C8/14
摘要： A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.
摘要翻译：本文公开了一种字线激活延迟监视器电路，其包括位于存储器的数据存储阵列内的采样字线，其中采样字线由存储器内具有基本相同结构或位置的电路选择或激活，该电路选择或激活数据存储阵列的字线。公开了一种电路，其通过激活位于第二子阵列组的数据存储阵列内的采样字线来确定存储器内的第一子阵列组的字线激活延迟。还公开了相应的方法。

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