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1. 发明授权

US6069815A Semiconductor memory having hierarchical bit line and/or word line architecture 失效
标题翻译：具有分层位线和/或字线架构的半导体存储器
公开(公告)号：US6069815A
公开(公告)日：2000-05-30
申请号：US993538
申请日：1997-12-18
申请人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
发明人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C7/18 , G11C8/14 , G11C16/06 , G11C5/06
CPC分类号： G11C7/18 , G11C8/14
摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.
摘要翻译：公开了具有分级位线和/或字线架构的半导体存储器。在一个实施例中，具有特别适合于小于8F2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。每列中的多个局部位线对耦合到存储器单元，其中至少一个局部位线耦合到主位线。在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

2. 发明授权

US06690198B2 Repeater with reduced power consumption 有权
标题翻译：中继器具有降低的功耗
公开(公告)号：US06690198B2
公开(公告)日：2004-02-10
申请号：US10114195
申请日：2002-04-02
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H03K190175
CPC分类号： H03K19/01721 , G11C7/1048 , G11C7/1069 , G11C11/4096 , H03K19/0013
摘要： A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.
摘要翻译：描述了具有改进的开关速度和降低的功耗的中继器电路。中继器电路被配置为从信号线的第一段接收输入信号，并且响应于主动控制信号将信号传递到信号线的第二段。

3. 发明授权

US5831912A Semiconductor memory having space-efficient layout 失效
标题翻译：半导体存储器具有节省空间的布局
公开(公告)号：US5831912A
公开(公告)日：1998-11-03
申请号：US938074
申请日：1997-09-26
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C11/401 , G11C5/02 , G11C7/18 , G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C7/00 , G11C7/02
CPC分类号： G11C5/025 , G11C11/4097 , G11C7/18
摘要： The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.
摘要翻译：本公开包括具有空间有效布局的半导体存储器。动态随机存取存储器（DRAM）芯片具有以行和列排列的多个存储单元（18）。半导体存储器包括设置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中每个读出放大器（14）设置在相关联的列（16）的读出放大器区域中，。多个放大器（124或126）由至少一个驱动器（140或142）驱动，多个放大器中的每个放大器设置在一对互补位线（120）之间并位于读出放大器区域内。至少一个驱动器至少与至少一个驱动器共享至少一个横向于列方向延伸的扩散区域，使得读出放大器组的触点数量减少。

4. 发明授权

US07146471B2 System and method for variable array architecture for memories 有权
标题翻译：用于存储器的可变阵列架构的系统和方法
公开(公告)号：US07146471B2
公开(公告)日：2006-12-05
申请号：US10748333
申请日：2003-12-31
申请人： Toshiaki Kirihata , Gerhard Mueller , Wing K. Luk
发明人： Toshiaki Kirihata , Gerhard Mueller , Wing K. Luk
IPC分类号： G06F12/02
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.
摘要翻译：公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

5. 发明授权

US6081479A Hierarchical prefetch for semiconductor memories 有权
标题翻译：半导体存储器的分层预取
公开(公告)号：US6081479A
公开(公告)日：2000-06-27
申请号：US333539
申请日：1999-06-15
申请人： Brian Ji , Toshiaki Kirihata , Gerhard Mueller , David Hanson
发明人： Brian Ji , Toshiaki Kirihata , Gerhard Mueller , David Hanson
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.
摘要翻译：根据本发明的半导体存储器包括包括多个分层级的数据路径，每个级包括与其他级不同的位数据速率。至少两个预取电路设置在各级之间。至少两个预取电路包括用于接收数据位并存储数据位的至少两个锁存器，直到层级中的下一级能够接收数据位。所述至少两个预取电路耦合在级之间，使得级之间每级的总体数据速率基本相等。控制信号控制至少两个锁存器，使得预取电路保持级之间的总体数据速率。

6. 发明授权

US5877994A Space-efficient MDQ switch placement 失效
标题翻译：节省空间的MDQ开关放置
公开(公告)号：US5877994A
公开(公告)日：1999-03-02
申请号：US938073
申请日：1997-09-26
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C11/403 , G11C7/06 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/02 , G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. An MDQ switch being located in a sense amplifier region occupying a corresponding row-wise space to the at least one driver to provide space efficient placement thereof.
摘要翻译：具有排列成行和列的多个存储单元的半导体存储器包括布置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中存储体中的每个读出放大器设置在读出放大器区域之间，一对相关列的互补位线。 MDQ开关位于感测放大器区域中，占据与至少一个驱动器相对应的行方向空间以提供空间高效的放置。

7. 发明授权

US5864496A High density semiconductor memory having diagonal bit lines and dual word lines 失效
标题翻译：具有对角位线和双字线的高密度半导体存储器
公开(公告)号：US5864496A
公开(公告)日：1999-01-26
申请号：US939455
申请日：1997-09-29
申请人： Gerhard Mueller , Toshiaki Kirihata , Heinz Hoenigschmid
发明人： Gerhard Mueller , Toshiaki Kirihata , Heinz Hoenigschmid
IPC分类号： H01L27/108 , G11C7/18 , G11C11/4097 , H01L21/8242 , G11C5/08
CPC分类号： H01L27/10891 , G11C11/4097 , G11C7/18 , H01L27/10861
摘要： The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.
摘要翻译：半导体存储器包括以行和列排列的存储器单元的存储单元阵列（10）和以沿存储单元阵列改变水平方向的图案布置的多个对角位线（BLP1-BLPN），以便于访问所述记忆细胞位线布置成与多条双字线（WL1-WLM）非正交，其中每个双字线包括第一层的主字线（MWLi）和多个本地字线（LWL1-LWLX）在第二层。本地字线经由多个间隔的电连接（29）连接到公共行的主字线，例如“缝合”结构中的电触点，并且每个本地字线连接到多个存储单元（MC ）。电连接沿着与位线的存储单元阵列基本上相同的图案运行。

8. 发明授权

US06335652B2 Method and apparatus for the replacement of non-operational metal lines in DRAMS 失效
标题翻译：用于替代DRAMS中的非操作金属线的方法和装置
公开(公告)号：US06335652B2
公开(公告)日：2002-01-01
申请号：US09764816
申请日：2001-01-18
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G05F1116
CPC分类号： G11C29/80 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.
摘要翻译：一种半导体集成电路器件，包括用于替换用于连接到电路块的非操作金属线的冗余金属线。本发明还包括一种用于将有缺陷或其它不可操作的导电数据线与其所连接的电路块分离的方法，以及通过将其连接到相同的电路块来用冗余线代替有缺陷的导电数据线。不需要备用导电块。冗余金属线可以在集成电路器件内的多个层级中使用。

9. 发明授权

US06292402B1 Prefetch write driver for a random access memory 失效
标题翻译：为随机存取存储器预取写入驱动程序
公开(公告)号：US06292402B1
公开(公告)日：2001-09-18
申请号：US09456589
申请日：1999-12-08
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C1604
CPC分类号： G11C7/1072 , G11C7/1078
摘要： A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.
摘要翻译：用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。数据级和使能级可以各自包括两个或多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。当数据通过数据阶段时，相应的使能状态通过使能阶段。如果使能状态指示要将数据级中的数据写入阵列，则将数据传送到RAM阵列。

10. 发明授权

US06272062B1 Semiconductor memory with programmable bitline multiplexers 有权
标题翻译：具有可编程位线多路复用器的半导体存储器
公开(公告)号：US06272062B1
公开(公告)日：2001-08-07
申请号：US09583596
申请日：2000-05-31
申请人： Gerhard Mueller , Toshiaki Kirihata , Dmitry Netis
发明人： Gerhard Mueller , Toshiaki Kirihata , Dmitry Netis
IPC分类号： G11C800
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C8/12 , G11C11/4097
摘要： There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.
摘要翻译：提供一种半导体存储器件，其包括：以至少两组布置的多个存储单元; 至少一个读出放大器; 第一和第二多路复用器; 和至少一个可编程控制装置。每个多路复用器适于将至少一个组耦合到放大器。可编程控制装置适于控制第一和第二多路复用器。在一个实施例中，可编程控制装置适于独立地控制多路复用器。

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