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101. 发明授权

US06751152B2 Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage 失效
标题翻译：方法和配置允许在增加具有存取晶体管阈值电压的感测信号的同时降低字线升压电压操作
公开(公告)号：US06751152B2
公开(公告)日：2004-06-15
申请号：US09999379
申请日：2001-10-31
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
IPC分类号： G11C800
CPC分类号： G11C11/4085 , G11C7/065 , G11C11/4091
摘要： A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.
摘要翻译：存储器阵列架构采用全Vdd位线预充电电压和低字线升压电压，其小于Vdd加上存取晶体管的阈值电压。在写入模式中，数据位的第一低电平几乎完全写入存储元件，然而数据位的第二高电平未完全写入存储元件。在读取模式下，数据位的第一低电平从存储元件完全读出，然而数据位的第二高电平不通过利用存取晶体管阈值电压被读出。这允许感测信号仅在第一电压电平传输到Vdd预充电BL。参考WL优选地用于产生用于差分Vdd感测方案的参考位线电压。或者，可以使用单个BL数字感测方案。降低字线电压通过节省Vpp发生器和支持电路上的功率以及减小Vpp发生器和支持电路的尺寸而降低功耗，并且消除了与Vpp电压相关的高电压问题，例如介质击穿和其他可靠性同时避免复杂的解码方案并节省成本。

102. 发明授权

US06683805B2 Suppression of leakage currents in VLSI logic and memory circuits 有权
标题翻译： VLSI逻辑和存储器电路中泄漏电流的抑制
公开(公告)号：US06683805B2
公开(公告)日：2004-01-27
申请号：US10067411
申请日：2002-02-05
申请人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
发明人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
IPC分类号： G11C11413
CPC分类号： G11C11/412
摘要： An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.
摘要翻译：提供一种SRAM系统，其具有包括至少一个接收第一电源电压的电池的SRAM单元阵列和用于向至少一个电路的至少一个选定电路提供第二电源电压的功率控制电路。该系统是存储器阵列和逻辑系统之一，并且至少一个电路的电路是存储器阵列的存储单元，存储器阵列的读出放大器和逻辑系统的路径之一。还提供了一种用于向系统的至少一个电路提供电源电压的方法。

103. 发明授权

US06617702B2 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权
标题翻译：半导体器件利用对准标记来全面对准半导体衬底的正面和背面
公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译：本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

104. 发明授权

US06426914B1 Floating wordline using a dynamic row decoder and bitline VDD precharge 有权
标题翻译：浮动字线使用动态行解码器和位线VDD预充电
公开(公告)号：US06426914B1
公开(公告)日：2002-07-30
申请号：US09839105
申请日：2001-04-20
申请人： Robert H. Dennard , Louis L. Hsu , Toshiaki K. Kirihata
发明人： Robert H. Dennard , Louis L. Hsu , Toshiaki K. Kirihata
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C7/22 , G11C8/10 , G11C11/4076 , G11C11/4085 , G11C11/4087
摘要： A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.
摘要翻译：短周期DRAM使用浮动字线，动态行解码器和位线VDD预充电，这提高了短周期DRAM（3-6ns）的阵列效率，而不损害其性能。提供了一种小尺寸字线驱动器电路，以减少短周期DRAM的行大小，而不会影响行访问时序。实现动态解码操作，其有意地允许一些未选择的字线在行访问期间浮动。 Vdd位线预充电/感测技术在行访问期间避免了对浮动字线的有害（或正）耦合效应。用于读取操作的Vdd数据线（或DQ）预充电以及输入数据时序的控制避免了写入操作的有害（或正）耦合效应。

105. 发明授权

US06410369B1 Soi-body selective link method and apparatus 失效
标题翻译：单体选择性联动方法及装置
公开(公告)号：US06410369B1
公开(公告)日：2002-06-25
申请号：US09591511
申请日：2000-06-12
申请人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
发明人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
IPC分类号： H01L2100
CPC分类号： H01L27/1104 , H01L27/1203
摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
摘要翻译：绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

106. 发明授权

US06228745B1 Selective reduction of sidewall slope on isolation edge 失效
标题翻译：隔离边缘侧壁倾斜的选择性减小
公开(公告)号：US06228745B1
公开(公告)日：2001-05-08
申请号：US09460134
申请日：1999-12-13
申请人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S438/947
摘要： Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.
摘要翻译：公开了一种半导体结构，其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。晶体管还包括栅电极，栅极氧化物和有源区。源极注入和漏极注入位于所述有源区的相对侧，并且所述栅极氧化物和栅电极位于所述有源区的顶部。晶体管还包括与所述有源区相邻的两个沟槽隔离，其中所述沟槽隔离位于所述有源区的相对侧，使得每个沟槽的侧壁用作与所述有源区的界面，所述沟槽的至少一个侧壁用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率，所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。

107. 发明授权

US06222244B1 Electrically blowable fuse with reduced cross-sectional area 失效
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

108. 发明授权

US06144054A DRAM cell having an annular signal transfer region 有权
标题翻译： DRAM单元具有环形信号传送区域
公开(公告)号：US06144054A
公开(公告)日：2000-11-07
申请号：US205934
申请日：1998-12-04
申请人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
发明人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.
摘要翻译：一种存储器件，形成在具有形成在衬底中的侧壁的沟槽的衬底中。该器件包括位线导体和字线导体。信号存储节点具有形成在沟槽内的第一电极，第二电极和形成在第一和第二电极之间的节点电介质。信号传递装置具有：（i）环形信号传递区域，其外表面邻近沟槽的侧壁，内表面，第一端和第二端; （ii）将信号传送区域的第一端耦合到第一扩散区域。信号存储节点的第二电极; （iii）将信号传输区域的第二端耦合到位线导体的第二扩散区域; （iv）涂覆信号传送区域的内表面的栅极绝缘体; 和（v）涂覆栅极绝缘体并耦合到字线的栅极导体。导电连接构件将信号传递区域耦合到参考电压以减少浮体效应。

109. 发明授权

US06015991A Asymmetrical field effect transistor 失效
标题翻译：非对称场效应晶体管
公开(公告)号：US06015991A
公开(公告)日：2000-01-18
申请号：US820401
申请日：1997-03-12
申请人： Donald C. Wheeler , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L21/027 , H01L21/266 , H01L21/3213 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/78 , H01L29/02
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/32139 , H01L29/42376 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L21/0274
摘要： Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.
摘要翻译：公开了一种非对称场效应晶体管，其包括用作源极的第一区域，用作漏极的第二区域，薄栅极氧化物和栅电极。栅电极是不对称的，其侧壁之一是倾斜的。第二区域在所述倾斜侧壁的下方延伸。在所述栅电极下方延伸的所述第二区域的部分比所述第二区域的剩余部分掺杂少。此外，所述第二区域在所述栅电极下方具有倾斜的接合边缘。

110. 发明授权

US5770875A Large value capacitor for SOI 失效
标题翻译： SOI的大值电容器
公开(公告)号：US5770875A
公开(公告)日：1998-06-23
申请号：US724287
申请日：1996-09-16
申请人： Fariborz Assaderaghi , Louis L. Hsu , Jack A. Mandelman , William R. Tonti
发明人： Fariborz Assaderaghi , Louis L. Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/334 , H01L21/84 , H01L29/786 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/84
摘要： Large capacitance, low-impedance decoupling capacitors in SOI and their method of fabrication. A high conductivity trench substrate contact is made adjacent to the capacitor by removal of insulator lining the capacitor by use of an extra mask thereby making a substrate contact when the trench is filled with doped polysilicon. The inventive process is compatible with and easily integrated into existing SOI logic technologies. The SOI decoupling capacitors are formed in trenches which pass through the silicon and buried oxide layers and into the underlying silicon substrate.
摘要翻译： SOI中的大电容，低阻抗去耦电容及其制造方法。通过使用额外的掩模去除夹在电容器上的绝缘体，使与电容器相邻的高导电性沟槽衬底接触，从而当沟槽填充有掺杂多晶硅时进行衬底接触。本发明的方法与现有的SOI逻辑技术兼容并容易地集成。 SOI去耦电容器形成在通过硅和掩埋氧化物层并进入下面的硅衬底的沟槽中。

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