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91. 发明授权

US06818975B1 ELECTRIC CHARGE GENERATING SEMICONDUCTOR SUBSTRATE BUMP FORMING DEVICE, METHOD OF REMOVING ELECTRIC CHARGE FROM ELECTRIC CHARGE GENERATING SEMICONDUCTOR SUBSTRATE DEVICE FOR REMOVING ELECTRIC CHARGE FROM ELECTRIC CHARGE GENERATING SEMICONDUCTOR SUBSTRATE, AND ELECTRIC CHARGE GENERATING SEMICONDUCTOR SUBSTRATE 失效
标题翻译：电荷生成半导体基板保存形成装置的方法，从电荷产生电子基板去除电荷的方法，用于从电荷产生半导体基板去除电荷和电荷产生半导体基板
公开(公告)号：US06818975B1
公开(公告)日：2004-11-16
申请号：US10019700
申请日：2002-01-02
申请人： Shoriki Narita , Yasutaka Tsuboi , Masahiko Ikeya , Takaharu Mae , Shinji Kanayama
发明人： Shoriki Narita , Yasutaka Tsuboi , Masahiko Ikeya , Takaharu Mae , Shinji Kanayama
IPC分类号： H01L2302
CPC分类号： H01L21/67144 , H01L21/67138
摘要： The present invention provides a bump forming apparatus (101, 501) which can prevent charge appearance semiconductor substrates (201, 202) from pyroelectric breakdown and physical failures, a method carried out by the bump forming apparatus for removing charge of charge appearance semiconductor substrates, a charge removing unit for charge appearance semiconductor substrates, and a charge appearance semiconductor substrate. At least when the wafer is cooled after the bump bonding is connected on the wafer, electric charge accumulated on the wafer (202) because of the cooling is removed through direct contact with a post-forming bumps heating device (170), or the charge is removed by a decrease in temperature control so that charge can be removed in a noncontact state. Therefore, an amount of charge of the wafer can be reduced in comparison with the conventional art, so that the wafer is prevented from pyroelectric breakdown and damage such as a break or the like to the wafer itself.
摘要翻译：本发明提供一种可防止电荷外观半导体衬底（201,202）发生热释电和物理故障的凸块形成装置（101,501），用于去除电荷外观半导体衬底的电荷的凸块形成装置执行的方法，用于电荷外观半导体衬底的电荷去除单元和电荷外观半导体衬底。至少当在晶片上连接凸起接合之后晶片被冷却时，由于冷却而积聚在晶片（202）上的电荷通过与后成形凸块加热装置（170）直接接触而被去除，或者电荷通过降低温度控制来去除，从而可以在非接触状态下去除电荷。因此，与传统技术相比，可以减少晶片的电荷量，从而防止晶片对晶片本身的热释电和损坏（例如断裂等）。

92. 发明授权

US06815809B2 Portable electronic device 有权
标题翻译：便携式电子设备
公开(公告)号：US06815809B2
公开(公告)日：2004-11-09
申请号：US10276199
申请日：2002-11-12
申请人： Bente Adriaan Bordes , Cornelis Maria Hart
发明人： Bente Adriaan Bordes , Cornelis Maria Hart
IPC分类号： H01L2302
CPC分类号： H01L23/48 , G06K19/07749 , G06K19/07788 , H01L2924/0002 , H01L2924/00
摘要： The electronic device (10) comprises an integrated circuit (30) with a first (18) and a second side (19), on both sides (18, 19) of which first and second conductive areas (31, 32) are present. The electronic device (10) further has a first (64) and a second (65) conductive structure, which (64, 65) are present on a—preferably enveloping—layer (71) of dielectric material. Signal and power to and from the integrated circuit (30) are transferred through capacitors (11, 12) formed by the conductive areas (31, 32) and the conductive structures (64, 65) and an intermediate layer (73, 74) of dielectric material. The integrated circuit (30) may contain a protective layer (33) in the second conductive area (32).
摘要翻译：电子设备（10）包括在其两侧（18,19）上具有第一和第二侧面（19）的第一和第二侧面（19）的集成电路（30），其中存在第一和第二导电区域（31,32）。电子器件（10）还具有第一（64）和第二（65）导电结构，其中（64,65）存在于电介质材料的优选包络层（71）上。来自集成电路（30）的信号和功率通过由导电区域（31,32）和导电结构（64,65）形成的电容器（11,12）和中间层（73,74）介电材料。集成电路（30）可以在第二导电区域（32）中包含保护层（33）。

93. 发明授权

US06809410B2 Power semiconductor module 有权
标题翻译：功率半导体模块
公开(公告)号：US06809410B2
公开(公告)日：2004-10-26
申请号：US09828947
申请日：2001-04-10
申请人： Junji Yamada
发明人： Junji Yamada
IPC分类号： H01L2302
CPC分类号： H01L23/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/45124 , H01L2224/48091 , H01L2224/48137 , H01L2224/49 , H01L2924/01013 , H01L2924/01014 , H01L2924/15787 , H01L2924/181 , H01R4/30 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A power semiconductor module with a connection structure in which an electrode terminal whose one end is connected with an electric power semiconductor device which is resin sealed inside of the case, is exposed along an outer surface of a case for taking out electrode from the semiconductor device, and is electrically connected to an electrode for external connection disposed on the electrode terminal, wherein a female screw hole for screwing is provided on side of the outer surface of the case, a male screw member formed at its opposite ends with screw threads is threadedly engaged with the female screw hole through the electrode terminal.
摘要翻译：一种具有连接结构的功率半导体模块，其一端与树脂密封在壳体内部的电力半导体器件连接的电极端子沿着从半导体器件取出电极的外壳的外表面露出并且电连接到设置在电极端子上的用于外部连接的电极，其中用于旋拧的阴螺纹孔设置在壳体的外表面的侧面上，在其相对端用螺纹形成的阳螺纹构件是螺纹的通过电极端子与阴螺纹孔啮合。

94. 发明授权

US06806562B2 Device with at least one semiconductor component and a printed circuit board and method of establishing an electromechanical connection between the two 失效
标题翻译：具有至少一个半导体部件和印刷电路板的装置以及在两者之间建立机电连接的方法
公开(公告)号：US06806562B2
公开(公告)日：2004-10-19
申请号：US10057127
申请日：2002-01-25
申请人： Bernd Barchmann , Erik Heinemann , Josef Heitzer , Frank Pueschner
发明人： Bernd Barchmann , Erik Heinemann , Josef Heitzer , Frank Pueschner
IPC分类号： H01L2302
CPC分类号： H01L21/563 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16235 , H01L2224/16237 , H01L2224/73203 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2224/81898 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K1/113 , H05K3/325 , H05K2201/0969 , H05K2201/10674 , H05K2201/209 , H01L2224/05639 , H01L2924/00014
摘要： A device having a semiconductor component and a printed circuit board are described. The semiconductor component has external contacts and the printed circuit board has contact terminals. The contact terminals display a central blind opening, into which the external contacts of the semiconductor component protrude and are in a force-locking engagement with the contact terminal areas. In the method of electromechanically connecting the two parts to form a device, after they have been aligned, the two components are merely pressed onto each other.
摘要翻译：描述具有半导体部件和印刷电路板的器件。半导体元件具有外部触点，并且印刷电路板具有接触端子。接触端子显示中央盲孔，半导体部件的外部触点突出并且与接触端子区域形成力锁定接合。在机电地连接两部分以形成装置的方法中，在它们对准之后，两个部件仅被压在彼此上。

95. 发明授权

US06798054B1 Method of packaging multi chip module 有权
标题翻译：多芯片封装方法
公开(公告)号：US06798054B1
公开(公告)日：2004-09-28
申请号：US09627979
申请日：2000-07-28
申请人： Randy H. Y. Lo , Chi-Chuan Wu , Ssu-Cheng Lai
发明人： Randy H. Y. Lo , Chi-Chuan Wu , Ssu-Cheng Lai
IPC分类号： H01L2302
CPC分类号： H01L25/105 , H01L25/03 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1005 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/05599
摘要： A method of packaging a multi chip module (MCM) with low cost and high reliability is disclosed. In the MCM process, a plurality of bare chips and CPSs, such as CPU or memory device, are integrated on a substrate to increase the package density. The method discards the high cost KGD process and directly takes the thin and small CSPs passing the tests as KGD and integrates the chips and CSPs into ball grid array package (BGA package) so that the cost is reduced and the yield and quality of the package is improved.
摘要翻译：公开了一种以低成本和高可靠性封装多芯片模块（MCM）的方法。在MCM过程中，多个裸芯片和CPS（例如CPU或存储器件）集成在基板上以增加封装密度。该方法丢弃高成本的KGD过程，并直接将薄型和小型CSP作为KGD通过测试，并将芯片和CSP集成到球栅阵列封装（BGA封装）中，从而降低成本，并且封装的产量和质量改进了

96. 发明授权

US06791175B2 Stacked type semiconductor device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US06791175B2
公开(公告)日：2004-09-14
申请号：US10255960
申请日：2002-09-27
申请人： Mie Matsuo , Kenichi Imamiya
发明人： Mie Matsuo , Kenichi Imamiya
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L23/544 , H01L2223/5444 , H01L2224/16145 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596
摘要： Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
摘要翻译：公开了一种具有多个半导体集成电路芯片堆叠的叠层型半导体器件，每个半导体集成电路芯片包括保持电路，该保持电路保持电子写入芯片中的关于芯片的识别信息，设置识别信息的识别信息设置电路关于芯片，在多个半导体集成电路芯片已被堆叠之后的保持电路中，以及至少一个设置终端，用于在保持电路中设置关于芯片的识别信息，其中至少一个设置终端半导体集成电路芯片连接到任何其它半导体集成电路芯片的至少一个相应的设置端子。

97. 发明授权

US06791173B2 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06791173B2
公开(公告)日：2004-09-14
申请号：US10441123
申请日：2003-05-20
申请人： Toru Saga
发明人： Toru Saga
IPC分类号： H01L2302
CPC分类号： H01L24/97 , H01L21/561 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/05599 , H01L2224/16 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In order to manufacture a thin and small semiconductor device at low cost, the semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises: a film wiring substrate made of insulating resin; a semiconductor chip fixed to the main surface of the wiring substrate; conductive wires to connect terminals of the semiconductor chip and wirings on the main surface of the wiring substrate; an encapsulation made of insulating resin integrally laminated on the main surface of the wiring substrate and covering the semiconductor chip and the bonding wires; and conductors penetrating through the wiring substrate and having one ends connected to the wirings on the main surface of the wiring substrate and the other ends protruding to the rear surface of the wiring substrate to form external terminals formed of bump electrodes, wherein the external terminals form the ball grid array. The thickness of the semiconductor chip (100 &mgr;m or smaller) is larger than that of the wiring substrate (70 &mgr;m or smaller), and the thickness of the wiring substrate is larger than the external terminal (30 &mgr;m or smaller). The thickness of the semiconductor device is 0.5 mm or smaller.
摘要翻译：为了以低成本制造薄型和小型半导体器件，公开了半导体器件及其制造方法。半导体器件包括：由绝缘树脂制成的膜布线基板; 固定到所述布线基板的主表面的半导体芯片; 导电线将半导体芯片的端子和布线基板的主表面上的布线连接起来; 由绝缘树脂制成的封装体，一体层压在布线基板的主表面上并覆盖半导体芯片和接合线; 以及导体穿过布线基板，并且其一端连接到布线基板的主表面上的布线，另一端突出到布线基板的后表面，以形成由凸块电极形成的外部端子，其中外部端子形成球栅阵列。半导体芯片的厚度（100μm以下）大于布线基板（70μm以下）的厚度，布线基板的厚度大于外部端子（30μm以下）。半导体器件的厚度为0.5mm以下。

98. 发明授权

US06784527B2 Electronic card formed of a double-sided printed circuit board with static electricity prevention circuit 失效
标题翻译：电子卡由具有静电防止电路的双面印刷电路板组成
公开(公告)号：US06784527B2
公开(公告)日：2004-08-31
申请号：US10252798
申请日：2002-09-24
申请人： Minoru Fukunaga
发明人： Minoru Fukunaga
IPC分类号： H01L2302
CPC分类号： G06K19/07735 , H05K1/0259 , H05K3/242 , H05K3/281 , H05K2201/0352 , H05K2201/09709 , H05K2201/09781
摘要： Charge prevention patterns disposed on one surface of a circuit board and electrolytic plating patterns disposed on the other surface of the circuit board are disposed in a zigzag pattern in end surfaces of the substrate. The thickness of a coating layer is smaller than the thickness of a card case.
摘要翻译：设置在电路板的一个表面上的电荷防止图案和布置在电路板的另一个表面上的电解电镀图案以Z字形图案设置在基板的端面中。涂层的厚度小于卡盒的厚度。

99. 发明授权

US06784367B2 Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies 有权
公开(公告)号：US06784367B2
公开(公告)日：2004-08-31
申请号：US10374449
申请日：2003-02-25
申请人： Ernest J. Russell , Bharath Nagabhushanam , Terry Lee , Roger Norwood
发明人： Ernest J. Russell , Bharath Nagabhushanam , Terry Lee , Roger Norwood
IPC分类号： H01L2302
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49541 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates. Each conductive member can have a first end with a bond-site proximate to a corresponding bond-pad of the die, a second end defining an external connector, and an elongated conductive section connecting the bond-site to the external connector. The conductive members are generally arranged so that at least some of the bond-sites are arranged in a first row in which the bond-sites and a portion of the elongated sections are spaced apart from one other by a first gap width. The support structure can more specifically include a first conductive member having a first bond-site coupled to the Vref bond-pad by a first wire-bond line and a second conductive member having a second bond-site coupled to the signal bond-pad by a second wire-bond line. The first bond-site of the first conductive member can be spaced apart from the second bond-site of the second conductive member by a second gap width greater than the first gap width.

100. 发明授权

US06781226B2 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
标题翻译：可重构处理器模块包括混合堆叠集成电路芯片元件
公开(公告)号：US06781226B2
公开(公告)日：2004-08-24
申请号：US10452113
申请日：2003-06-02
申请人： Jon M. Huppenthal , D. James Guzy
发明人： Jon M. Huppenthal , D. James Guzy
IPC分类号： H01L2302
CPC分类号： G06F15/7867 , H01L25/18 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.
摘要翻译：一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的触点互相连接，死了所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。

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