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1. 发明申请

US20130157639A1 MOBILE ELECTRONIC DEVICES UTILIZING RECONFIGURABLE PROCESSING TECHNIQUES TO ENABLE HIGHER SPEED APPLICATIONS WITH LOWERED POWER CONSUMPTION 审中-公开
标题翻译：移动电子设备利用可重构处理技术实现更低功耗的高速应用
公开(公告)号：US20130157639A1
公开(公告)日：2013-06-20
申请号：US13365090
申请日：2012-02-02
申请人： Jon M. Huppenthal , Thomas R. Seeman , Jeffrey Hammes , D. James Guzy
发明人： Jon M. Huppenthal , Thomas R. Seeman , Jeffrey Hammes , D. James Guzy
IPC分类号： H04W4/00
CPC分类号： G06F1/3234 , G06F17/5054 , G06F2217/78 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： Disclosed herein are mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption for, inter alia, increased device battery life. The techniques disclosed herein enable greatly enhanced compression/decompression as well as encryption and decryption functionality to be provided in addition to overall greater processing capability particularly in those applications wherein minimization of power consumption is desired. Package-on-package and other assembly techniques may be used to provide the reconfigurable processor in a small footprint package.
摘要翻译：本文公开了使用可重构处理技术的移动电子设备，以便特别是增加设备电池寿命来实现具有降低的功率消耗的更高速度应用。除了总体更大的处理能力之外，本文公开的技术能够大大增强压缩/解压缩以及加密和解密功能，特别是在需要最小化功耗的那些应用中。封装封装和其他装配技术可用于以小尺寸封装提供可重构处理器。

2. 发明授权

US07282951B2 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
标题翻译：可重构处理器模块包括混合堆叠集成电路芯片元件
公开(公告)号：US07282951B2
公开(公告)日：2007-10-16
申请号：US11383149
申请日：2006-05-12
申请人： Jon M. Huppenthal , D. James Guzy
发明人： Jon M. Huppenthal , D. James Guzy
IPC分类号： H03K19/173 , H01L23/02
CPC分类号： H01L25/0657 , G06F15/7867 , H01L23/481 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.
摘要翻译：一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的触点互相连接，死了所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。

3. 发明授权

US07126214B2 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
公开(公告)号：US07126214B2
公开(公告)日：2006-10-24
申请号：US10802067
申请日：2004-03-16
申请人： Jon M. Huppenthal , D. James Guzy
发明人： Jon M. Huppenthal , D. James Guzy
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G06F15/7867 , H01L23/481 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

4. 发明授权

US06627985B2 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
标题翻译：可重构处理器模块包括混合堆叠集成电路芯片元件
公开(公告)号：US06627985B2
公开(公告)日：2003-09-30
申请号：US10012057
申请日：2001-12-05
申请人： Jon M. Huppenthal , D. James Guzy
发明人： Jon M. Huppenthal , D. James Guzy
IPC分类号： H01L2302
CPC分类号： G06F15/7867 , H01L25/18 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.
摘要翻译：一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的触点互相连接，死了所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。

5. 再颁专利

USRE42035E1 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
标题翻译：可重构处理器模块包括混合堆叠集成电路芯片元件
公开(公告)号：USRE42035E1
公开(公告)日：2011-01-18
申请号：US12178511
申请日：2008-07-23
申请人： Jon M. Huppenthal , D. James Guzy
发明人： Jon M. Huppenthal , D. James Guzy
IPC分类号： H01L23/02 , H05K7/06
CPC分类号： G06F15/7867 , H01L25/18 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.
摘要翻译：一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的接触互连，死了所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。

6. 发明授权

US06781226B2 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
标题翻译：可重构处理器模块包括混合堆叠集成电路芯片元件
公开(公告)号：US06781226B2
公开(公告)日：2004-08-24
申请号：US10452113
申请日：2003-06-02
申请人： Jon M. Huppenthal , D. James Guzy
发明人： Jon M. Huppenthal , D. James Guzy
IPC分类号： H01L2302
CPC分类号： G06F15/7867 , H01L25/18 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.
摘要翻译：一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的触点互相连接，死了所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。

7. 发明申请

US20060195729A1 RECONFIGURABLE PROCESSOR MODULE COMPRISING HYBRID STACKED INTEGRATED CIRCUIT DIE ELEMENTS 有权
标题翻译：包含混合堆叠集成电路元件的可重构处理器模块
公开(公告)号：US20060195729A1
公开(公告)日：2006-08-31
申请号：US11383149
申请日：2006-05-12
申请人： Jon Huppenthal , D. James Guzy
发明人： Jon Huppenthal , D. James Guzy
IPC分类号： G06F11/00
CPC分类号： H01L25/0657 , G06F15/7867 , H01L23/481 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.
摘要翻译：一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的触点互相连接，死了所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。

8. 发明授权

US4841526A Data communications system 失效
标题翻译：数据通信系统
公开(公告)号：US4841526A
公开(公告)日：1989-06-20
申请号：US932926
申请日：1986-11-19
申请人： Jon C. Wilson , David A. Shick , Robert L. Haynie , Donald R. Wilder , Larry D. Zimmerman , Richard M. LeCour , D. James Guzy
发明人： Jon C. Wilson , David A. Shick , Robert L. Haynie , Donald R. Wilder , Larry D. Zimmerman , Richard M. LeCour , D. James Guzy
IPC分类号： H04B7/185 , H04L1/00 , H04L1/16 , H04L1/18
CPC分类号： H04L1/0016 , H04B7/18582 , H04L1/0007 , H04L1/1607 , H04L1/1621 , H04L1/1806 , H04L1/1809 , H04L1/1832 , H04L1/1664
摘要： A data communications system employing sliding window protocol where the size of the window of the sending or receiving station can be made selectable by the user according to the speed, length or error rate of the communication link or the frame size used to maximize the utilization of the communication link. The negative acknowledgements sent by the receiving station specifies the upper and lower limit of a range of identification numbers of frames unsuccessfully received to increase efficiency. Before data is transmitted, the sending and receiving stations exchange the preferred sets of link parameters and generate a modified set of link parameters to resolve potential conflicts. Either the sending or the receiving station stores a table defining the frame sizes for use with different bit error rates of the communication link. The station then evaluates the current bit error rate to select the optimum frame size from the table and adjust the frame size accordingly.
摘要翻译：一种采用滑动窗口协议的数据通信系统，其中可以根据通信链路的速度，长度或错误率或发送或接收台的窗口的大小使用户可以选择用于最大限度地利用通信链接。接收站发送的否定确认指定了未成功接收到的帧的识别号码的范围的上限和下限，以提高效率。在发送数据之前，发送和接收站交换优选的链路参数集合，并生成一组修改的链路参数以解决潜在的冲突。发送站或接收站都存储定义与通信链路的不同比特错误率一起使用的帧大小的表。该站然后评估当前比特错误率，从表中选择最佳帧大小，并相应地调整帧大小。

9. 发明授权

US4034819A Electromagnetic compensating balance 失效
标题翻译：电磁补偿平衡
公开(公告)号：US4034819A
公开(公告)日：1977-07-12
申请号：US641152
申请日：1975-12-15
申请人： Clifford B. Akers , Roy A. Applequist , James E. Applequist , D. James Guzy
发明人： Clifford B. Akers , Roy A. Applequist , James E. Applequist , D. James Guzy
IPC分类号： G01G7/04 , G01G7/00
CPC分类号： G01G7/04
摘要： An electromagnetic compensating balance for the measurement of forces having a permanent magnet circuit assembly with an annular enclosed housing and with a central core defining a narrow annular air gap between a portion of the housing and core, and having a movable bobbin concentrically arranged around the core with a coil located in the air gap, the bobbin having end portions projecting above and below the housing which are connected to leaf support members for independent support of the bobbin from the magnet assembly, the upper end portions being connected to a weighing pan for weighing samples. The balance has sensing means comprising a first pair of capacitor rings located above said coil and a second pair of capacitor rings located below said bobbin connected in a manner which eliminates canting effects in said bobbin from a reference position, said sensing means generating a transducer output voltage representing an analog to displacements in the bobbin, said output voltage controlling a servo system for generating a d.c. current through the coil which activates the coil to create a compensating equilibrium force by the bobbin opposing the force of the weighing sample, the servo system having circuit means for providing an analog voltage representing current level said analog voltage controlling an analog to digital measuring circuit which operates with said servo circuit means but is independent thereto.
摘要翻译：一种用于测量具有环形封闭壳体的永磁体电路组件的电磁补偿平衡，并且具有在壳体和芯部的一部分之间限定窄环形空气间隙的中心芯，并且具有围绕芯部同心设置的可移动筒管线圈具有位于气隙中的线圈，线轴具有突出在壳体上方和下方的端部，该端部连接到叶片支撑构件，用于从磁体组件独立地支撑线轴，上端部连接到用于称重的称重盘样品。该天平具有检测装置，其包括位于所述线圈上方的第一对电容器环和位于所述线轴下方的第二对电容器环，其以从消除所述线轴的参考位置的倾斜效应的方式连接，所述感测装置产生换能器输出代表线圈中的位移的模拟电压，所述输出电压控制用于产生直流的伺服系统电流通过线圈，其激活线圈以产生与所述线轴相反的称重样品的补偿平衡力，所述伺服系统具有用于提供表示电流水平的模拟电压的电路装置，所述模拟电压控制模拟电压，所述模拟电压控制模拟到数字测量电路，与所述伺服电路装置一起操作，但与其无关。

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