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91. 发明申请

US20030162386A1 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20030162386A1
公开(公告)日：2003-08-28
申请号：US10240330
申请日：2003-03-06
发明人： Tsuyoshi Ogawa , Yuji Nishitani , Akihiko Okubora
IPC分类号： H01L051/40 , H01L021/301 , H01L021/46 , H01L021/78 , H01L021/4763 , H01L023/48 , H01L023/52 , H01L029/40
CPC分类号： H05K3/4682 , H01L21/4846 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/1531 , H01L2924/18161 , H01L2924/19105 , H01L2924/19106 , H01L2924/3025 , H05K1/0237 , H05K1/0306 , H05K1/0313 , H05K1/095 , H05K1/16 , H05K1/162 , H05K1/165 , H05K1/167 , H05K1/183 , H05K3/0052 , H05K3/20 , H05K3/205 , H05K3/4605 , H05K3/4614 , H05K3/4644 , H05K3/467 , H05K3/4688 , H05K2201/09509 , H05K2201/09763 , H05K2203/016 , H05K2203/061 , H05K2203/1189 , H01L2924/00
摘要： A wiring circuit block (2) is produced by forming a release layer (6) on one of planarized principal surfaces of a mother substrate (1), forming an insulating layer (7) on the release layer (6), patterning the insulating layer (7) and forming a wiring layer (8) on the patterned insulating layer (7), and separating the insulating layer (7) and wiring layer (8) from the release layer (6) on the mother substrate (1). The circuit block (2) has components (12), (13) and (17) deposited on the wiring layer (8), and is mounted on a base circuit board (3) to provide a wiring device. Also, semiconductor chips (62) are mounted on the circuit block (2), and the circuit block (2) is mounted on a base circuit board (64) to provide a semiconductor device.
摘要翻译：通过在母基板（1）的平坦化主面之一上形成剥离层（6），在剥离层（6）上形成绝缘层（7）而形成布线电路块（2），对绝缘层（7），并且在图案化绝缘层（7）上形成布线层（8），并将绝缘层（7）和布线层（8）与母基板（1）上的剥离层（6）分离。电路块（2）具有沉积在布线层（8）上的部件（12），（13）和（17），并且安装在基板（3）上以提供布线装置。此外，半导体芯片（62）安装在电路块（2）上，并且电路块（2）安装在基底电路板（64）上以提供半导体器件。

92. 发明申请

US20030157779A1 Method for applying adjusting marks on a semiconductor disk 有权
标题翻译：在半导体盘上应用调整标记的方法
公开(公告)号：US20030157779A1
公开(公告)日：2003-08-21
申请号：US10333453
申请日：2003-01-21
发明人： Wolfgang Diewald , Klaus Mummler
IPC分类号： H01L021/76 , H01L021/46 , H01L023/544 , H01L021/78 , H01L021/301
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.
摘要翻译：本发明涉及一种在半导体盘上应用调整标记的方法。在广泛的金属层中产生由非金属构成的小部分结构，随后在化学和机械抛光的帮助下，半导体盘随后在所述区域中被平面化。金属层中的结构尺寸和化学 - 机械抛光工艺相互调节，使得小部分非金属结构在抛光后突出在广泛的金属层之上。

93. 发明申请

US20030129810A1 Apparatus and processes for the mass production of photovoltaic modules 审中-公开
标题翻译：光伏组件批量生产的设备和工艺
公开(公告)号：US20030129810A1
公开(公告)日：2003-07-10
申请号：US10200265
申请日：2002-07-22
发明人： Kurt L. Barth , Robert A. Enzenroth , Walajabad S. Sampath
IPC分类号： H01L021/00 , H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L31/1828 , Y02E10/543
摘要： An apparatus and processes for large scale inline manufacturing of CdTe photovoltaic modules in which all steps, including rapid substrate heating, deposition of CdS, deposition of CdTe, CdCl2 treatment, and ohmic contact formation, are performed within a single vacuum boundary at modest vacuum pressures. A pnull ohmic contact region is formed by subliming a metal salt onto the CdTe layer. A back electrode is formed by way of a low cost spray process, and module scribing is performed by means of abrasive blasting or mechanical brushing through a mask. The vacuum process apparatus facilitates selective heating of substrates and films, exposure of substrates and films to vapor with minimal vapor leakage, deposition of thin films onto a substrate, and stripping thin films from a substrate. A substrate transport apparatus permits the movement of substrates into and out of vacuum during the thin film deposition processes, while preventing the collection of coatings on the substrate transport apparatus itself.
摘要翻译：一种用于大规模在线制造CdTe光伏模块的设备和方法，其中包括快速衬底加热，CdS沉积，CdTe沉积，CdCl 2处理和欧姆接触形成的所有步骤在适当的真空压力下在单个真空边界内进行。通过将金属盐升华到CdTe层上而形成p +欧姆接触区域。通过低成本喷涂工艺形成背面电极，并通过喷砂或机械刷涂通过掩模进行模块划线。真空处理装置有助于基板和薄膜的选择性加热，基板和薄膜暴露于蒸汽，蒸汽泄漏最小，薄膜沉积到基板上，以及从基板剥离薄膜。基板输送装置允许在薄膜沉积工艺期间将基板移入和移出真空，同时防止基板输送装置本身上的涂层的收集。

94. 发明申请

US20030077878A1 Method for dicing a semiconductor wafer 有权
公开(公告)号：US20030077878A1
公开(公告)日：2003-04-24
申请号：US10035372
申请日：2001-10-19
申请人： Applied Materials, Inc.
发明人： Ajay Kumar , Padmapani C. Nallan , Anisul Khan , Dragan V. Podlesnik
IPC分类号： H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L21/304 , H01L21/78
摘要： A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

95. 发明申请

US20020197770A1 Method of manufacturing semiconductor chips 失效
标题翻译：制造半导体芯片的方法
公开(公告)号：US20020197770A1
公开(公告)日：2002-12-26
申请号：US09987253
申请日：2001-11-14
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Masaaki Irie
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50 , H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/3185 , H01L24/97 , H01L2221/68327 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/73104 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/14 , H01L2224/0401
摘要： The method of manufacturing semiconductor chips includes adhering a sheet that is to be drawn to a reverse side of a semiconductor wafer on which an integrated circuit has been formed; separating individual semiconductor chips from the semiconductor wafer by dicing the semiconductor wafer from a front side along dicing lines; providing a sealing resin layer formed from an uncured sealing resin on upper surfaces of the semiconductor chips and in gaps between adjacent semiconductor chips, with the individual semiconductor chips maintained in a collected state, thereby sealing the semiconductor chips; and drawing the sheet, thereby separating the uncured sealing resin along the dicing lines.
摘要翻译：制造半导体芯片的方法包括将要拉制的片材粘附到已经形成集成电路的半导体晶片的背面; 通过沿着切割线从正面切割半导体晶片，从而将半导体芯片与半导体晶片分离; 在半导体芯片的上表面和相邻的半导体芯片之间的间隙中提供由未固化的密封树脂形成的密封树脂层，各个半导体芯片保持在收集状态，从而密封半导体芯片; 并拉伸片材，从而沿着切割线分离未固化的密封树脂。

96. 发明申请

US20020177288A1 SEMICONDUCTOR DEVICE SEPARATION USING A PATTERNED LASER PROJECTION 有权
标题翻译：使用图案激光投影的半导体器件分离
公开(公告)号：US20020177288A1
公开(公告)日：2002-11-28
申请号：US10114099
申请日：2002-04-02
发明人： Dr. Michael G. Brown , Dr. Ivan Eliashevich , Dr. Robert F. Karlicek Jr. , Mr. James E. Nering , Mr. Mark Gottfried
IPC分类号： H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： B23K26/0738 , B23K26/066 , B23K26/364 , B23K26/40 , B23K2101/40 , B23K2103/50 , H01L21/3043 , H01L21/6836 , H01L21/78 , H01L33/0095 , H01L2221/68327 , H01L2221/6834 , H01L2924/0002 , Y10S438/94 , H01L2924/00
摘要： Abstract of DisclosureA method for separating a semiconductor wafer into several thousand devices or die by laser ablation. Semiconductor wafers are initially pre-processed to create multiple devices, such as blue LEDs, on the wafers. The wafers are then mounted with tape coated with a generally high level adhesive. The mounted wafer is then placed on a vacuum chuck (which is itself positioned on a computer controlled positioning table) to hold it in place during the cutting process. The cutting surface is then covered with a protective layer to prevent contamination from the effluent resulting from the actual cutting process. A laser beam is generated and passed through optical elements and masks to create a pattern, such as a line or multiple lines. The patterned laser projection is directed at the wafer at a substantially normal angle and applied to the wafer until at least a partial cut is achieved through it. A mechanical separation process completes the separation when only a partial cut is achieved by the patterned laser projection. The die are then transferred to a grip ring for further processing.
摘要翻译：摘要公开通过激光烧蚀将半导体晶片分离成数千个器件或裸片的方法。半导体晶片最初被预处理以在晶片上产生多个器件，例如蓝色LED。然后将晶片安装在涂有一般高水平粘合剂的胶带上。然后将安装的晶片放置在真空吸盘（其本身位于计算机控制的定位台上），以在切割过程中将其保持在适当位置。然后用保护层覆盖切割表面，以防止来自实际切割过程的流出物的污染。生成激光束并通过光学元件和掩模以产生图案，例如线或多条线。图案化的激光投影以基本上正常的角度指向晶片，并施加到晶片，直到通过它至少实现部分切割。当通过图案化的激光投影仅实现部分切割时，机械分离过程完成分离。然后将模具转移到握环以进一步处理。

97. 发明申请

US20020098620A1 Chip scale package and manufacturing method thereof 审中-公开
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US20020098620A1
公开(公告)日：2002-07-25
申请号：US09767904
申请日：2001-01-24
发明人： Yi-Chuan Ding , Xin Hui Lee , Kun-Ching Chen
IPC分类号： H01L023/48 , H01L023/52 , H01L029/40 , H01L021/44 , H01L021/48 , H01L021/50 , H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L21/568 , H01L21/563 , H01L24/27 , H01L24/29 , H01L24/31 , H01L24/83 , H01L24/97 , H01L2221/6834 , H01L2224/04026 , H01L2224/05568 , H01L2224/05573 , H01L2224/1134 , H01L2224/131 , H01L2224/16225 , H01L2224/274 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/293 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/83191 , H01L2224/838 , H01L2224/83951 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/14 , H01L2924/15787 , H01L2924/30107 , Y10T29/49144 , Y10T29/49146 , Y10T29/49149 , Y10T29/49171 , H01L2224/81 , H01L2224/13099 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/05599
摘要： A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.
摘要翻译：芯片级封装主要包括通过各向异性导电粘合膜（ACF）附着到半导体芯片的有源表面的衬底。衬底在其下表面上设置有多个接触焊盘，并且在其上表面上设置有多个焊盘，其中接触焊盘电耦合到相应的焊盘。设置在基板的接触焊盘上的多个金属凸块。基板上的金属凸块通过ACF电耦合到芯片上的对应焊盘。衬底和ACF的侧面部分被密封在封装主体中。本发明还提供了一种使芯片级封装在晶片级的方法。该方法的特征在于一个接一个地将衬底附着到晶片的芯片上，以便大大减少与晶片与衬底之间的CTE不匹配相关的问题，从而显着提高产品产量。

98. 发明申请

US20020093076A1 Semiconductor device and method for producing the same by dicing 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20020093076A1
公开(公告)日：2002-07-18
申请号：US10091497
申请日：2002-03-07
发明人： Tetsuo Fujii , Tsuyoshi Fukada , Hiroshi Muto , Kenichi Ao , Shinji Yoshihara , Sumitomo Inomata
IPC分类号： H01L021/44 , H01L023/544 , H01L021/78
CPC分类号： H01L21/6836 , B29C33/0022 , B29C2043/023 , B81C1/00888 , B81C1/00896 , B81C2201/053 , H01L2221/68327 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/48095 , H01L2224/48465 , H01L2224/73265 , H01L2924/01057 , H01L2924/01068 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/16235 , H01L2924/30105 , H01L2924/00 , H01L2924/00014
摘要： A protective sheet is fixed to a jig, and regions of the protective sheet corresponding to regions where dicing-cut is to be performed are removed to form grooves. Then, a semiconductor wafer is bonded to the protective sheet at an opposite side of the jig, and the jig is detached from the protective sheet and the semiconductor wafer bonded together. After that, the semiconductor wafer is cut into semiconductor chips by dicing along the grooves of the protective sheet. Because the protective sheet is not cut by dicing, no scraps of the protective sheet is produced, thereby preventing contamination to the chips.
摘要翻译：将保护片固定在夹具上，除去对应于要进行切割的区域的保护片的区域，形成槽。然后，在夹具的相反侧将半导体晶片接合到保护片，并将夹具与保护片和半导体晶片接合在一起。之后，通过沿保护片的沟槽切割将半导体晶片切割成半导体芯片。由于保护片不是通过切割而切割的，所以不会产生保护片的废料，从而防止对芯片的污染。

99. 发明申请

US20020022343A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20020022343A1
公开(公告)日：2002-02-21
申请号：US09927403
申请日：2001-08-13
申请人： Fujitsu Quantum Devices Limited
发明人： Yasunori Nonaka
IPC分类号： H01L021/30 , H01L021/46 , H01L021/301 , H01L021/78
CPC分类号： H01L21/6835 , H01L21/764 , H01L21/78 , H01L23/482 , H01L23/522 , H01L24/48 , H01L24/49 , H01L2221/68377 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/13063 , H01L2924/3025 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： There are contained the steps of forming a plurality of semiconductor elements on surface sides of a plurality of operational unit areas defined on a semiconductor substrate respectively, then connecting the semiconductor elements only in the operational unit areas by wirings, and then forming recesses from the back side of the semiconductor substrate in the situation that a connection layer for connecting mechanically the semiconductor elements only in the operational unit areas is formed on the surface side of the semiconductor substrate, whereby the semiconductor substrate is separated between the semiconductor elements. Accordingly, there is provided a method of manufacturing a semiconductor device having a plurality of semiconductor elements, that is capable of preventing electrical interference between a plurality of semiconductor elements that are connected mutually via wirings and also suppressing variation a width of a recess that separates respective semiconductor elements.
摘要翻译：包含分别在半导体衬底上限定的多个操作单元区域的表面侧上形成多个半导体元件的步骤，然后仅通过布线在操作单元区域中连接半导体元件，然后从背面形成凹部在半导体衬底的表面侧上形成用于仅在操作单元区域中机械地连接半导体元件的连接层的半导体衬底的侧面，由此半导体衬底在半导体元件之间分离。因此，提供了一种制造具有多个半导体元件的半导体器件的方法，该半导体器件能够防止经由布线相互连接的多个半导体元件之间的电干扰，并且还抑制了分离各自的凹部的宽度的变化半导体元件。

100. 发明申请

US20020016047A1 Process for producing a large number of semiconductor chips from a semiconductor wafer 有权
公开(公告)号：US20020016047A1
公开(公告)日：2002-02-07
申请号：US09817248
申请日：2001-03-27
发明人： Toshiyuki Tateishi
IPC分类号： H01L021/30 , H01L021/46 , H01L021/301 , H01L021/78
CPC分类号： H01L21/78 , B28D5/022 , Y10S438/977
摘要： A process for producing a large number of semiconductor chips from a semiconductor wafer having a large number of rectangular areas defined by streets arranged on the front surface in a lattice form, semiconductor circuits being formed in the respective rectangular areas. This process comprises the steps of forming a plurality of grooves having a predetermined depth in the back surface of the semiconductor wafer, grinding the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer to a predetermined value and thereafter, cutting the semiconductor wafer along the streets to separate the rectangular areas from one another to obtain semiconductor chips.

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