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1. 发明申请

US20040248383A1 Method to reduce excess color filter signal deviation 失效
标题翻译：降低滤色器过滤信号偏差的方法
公开(公告)号：US20040248383A1
公开(公告)日：2004-12-09
申请号：US10456759
申请日：2003-06-06
发明人： Fu-Tien Weng , Yu-Kung Hsiao , Hung-Jen Hsu , Yi-Ming Dai , Chin-Chen Kuo , Te-Fu Tseng
IPC分类号： H01L021/78
CPC分类号： H01L27/14625 , H01L27/14621 , H01L27/14685
摘要： A method for processing a semiconductor substrate comprises the steps of: providing a substrate having a plurality of scribe lines arranged to form at least one filter region surrounded by the scribe lines, the scribe lines having a step height; at least partially filling the scribe lines with a resist material to reduce the step height of the scribe lines; and forming at least one color resist layer within the at least one filter region while the insoluble resist material remains in the scribe lines.
摘要翻译：一种用于处理半导体衬底的方法包括以下步骤：提供具有布置成形成被划线所包围的至少一个滤光区域的多个划线的衬底，划线具有台阶高度; 用抗蚀剂材料至少部分地填充划痕线以降低划线的台阶高度; 以及在所述至少一个过滤器区域内形成至少一个着色抗蚀剂层，同时所述不溶性抗蚀剂材料保留在划线中。

2. 发明申请

US20040214408A1 Method for forming scribe line on semiconductor wafer, and scribe line forming device 失效
标题翻译：在半导体晶片上形成划线的方法和划线生成装置
公开(公告)号：US20040214408A1
公开(公告)日：2004-10-28
申请号：US10483353
申请日：2004-06-09
发明人： Haruo Wakayama
IPC分类号： H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L23/544 , B23K26/40 , B23K2101/40 , B23K2103/50 , B28D1/221 , B28D5/00 , B28D5/0064 , H01L21/6836 , H01L2221/68327 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A silicon wafer 50 including a plurality of semiconductor devices patterned on a top surface thereof as a result of a wafer production process is prepared. A transparent film is applied on the top surface of the semiconductor wafer 50 so as to cover all the plurality of semiconductor devices. The semiconductor wafer with the transparent film is placed on a rotatable table 26 such that a rear surface of the semiconductor wafer not covered with the transparent film is facing up away from the rotatable table 26. The rear surface of the semiconductor wafer 50 is heated with a laser beam to form a laser spot, along a scribe line formation line for dividing the semiconductor wafer into a plurality of semiconductor chips, to a temperature lower than a softening point of the semiconductor wafer, while an area close to the laser spot is continuously cooled along the scribe line formation line.
摘要翻译：准备了包括由晶片制造工艺的结果在其顶表面上构图的多个半导体器件的硅晶片50。在半导体晶片50的上表面上涂敷透明膜，以覆盖所有多个半导体器件。具有透明膜的半导体晶片被放置在可旋转台26上，使得未被透明膜覆盖的半导体晶片的后表面朝向远离可旋转台26的上方。半导体晶片50的后表面被加热沿着用于将半导体晶片分割为多个半导体芯片的划线生成线形成激光束至激光点附近的区域的激光束至低于半导体晶片的软化点的温度沿划线形成线冷却。

3. 发明申请

US20040154733A1 Chip transfer method and apparatus 审中-公开
标题翻译：芯片传输方法和装置
公开(公告)号：US20040154733A1
公开(公告)日：2004-08-12
申请号：US10467584
申请日：2004-04-09
发明人： Thomas Morf
IPC分类号： B32B031/18 , H01L021/78
CPC分类号： H01L21/6835 , H01L24/75 , H01L24/83 , H01L2221/68309 , H01L2221/68322 , H01L2221/68354 , H01L2221/68359 , H01L2221/68368 , H01L2224/7598 , H01L2224/83 , H01L2224/95001 , H01L2224/95146 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01065 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H01S5/02272 , Y10T156/1179 , Y10T156/1911 , H01L2924/00
摘要： The invention is directed to a method for transferring an integrated-circuit element from a source substrate to a predetermined position on a target substrate. A source substrate with an integrated-circuit element on it and an element transfer holder with a layer of an adhesive material with a controllable adhesivity are provided. The element transfer holder is lowered onto the integrated-circuit element whereby the adhesivity has a first value suited to hold the integrated-circuit element to the element transfer holder. Then the integrated-circuit element is released from the source substrate and the element transfer holder with the integrated-circuit element attached to it is removed from the source substrate. The target substrate is provided with a droplet of a liquid arranged at the predetermined position and the element transfer holder is lowered with the integrated-circuit element attached to it onto the target substrate such that the integrated-circuit element gets into contact with the droplet. Then the adhesivity of the adhesive material is set to a second value suited to release the integrated-circuit element from the element transfer holder whereby the droplet aligns the integrated-circuit element to the predetermined position. Finally the element transfer holder is removed from the integrated-circuit element.
摘要翻译：本发明涉及将集成电路元件从源极基板转移到目标基板上的预定位置的方法。提供其上具有集成电路元件的源极衬底和具有可控粘合性的具有粘合剂材料层的元件转移保持器。元件转移保持器下降到集成电路元件上，由此粘合性具有适于将集成电路元件保持在元件转移支架上的第一值。然后，将集成电路元件从源极基板上释放，并且将与其连接的集成电路元件的元件转移支架从源极基板上去除。目标基板设置有布置在预定位置的液体液滴，并且元件转移保持器下降，集成电路元件附着到目标基板上，使得集成电路元件与液滴接触。然后将粘合剂材料的粘合性设定为适合于从元件转移保持器释放集成电路元件的第二值，由此液滴将集成电路元件对准到预定位置。最后，元件转移支架从集成电路元件移除。

4. 发明申请

US20040048419A1 Production method for semiconductor chip 有权
标题翻译：半导体芯片的生产方法
公开(公告)号：US20040048419A1
公开(公告)日：2004-03-11
申请号：US10250916
申请日：2003-07-08
发明人： Masahiko Kitamura , Koichi Yajima , Yusuke Kimura , Tomotaka Tabuchi
IPC分类号： H01L021/44 , H01L021/301 , H01L021/78
CPC分类号： H01L21/67132 , H01L21/3043 , H01L21/78 , Y10S438/977
摘要： A semiconductor wafer is applied to a support disk via an intervening adhesive layer 10 with the front side of the semiconductor wafer facing the adhesive layer, which is sensitive to a certain exterior factor for reducing its adhesive force; the semiconductor wafer is ground on the rear side; the wafer-and-support combination is applied to a dicing adhesive tape with the so ground rear side facing the dicing adhesive tape, which is surrounded and supported by the circumference by a dicing frame; the certain exterior factor is effected on the intervening adhesive layer to reduce its adhesive force; and the intervening adhesive layer and support disk are removed from the semiconductor wafer or chips without the possibility of damaging the same.
摘要翻译：将半导体晶片经由中间粘合剂层10施加到支撑盘上，其中半导体晶片的正面朝向粘合剂层，该粘合剂层对于某些外部因素敏感以降低其粘附力; 半导体晶片在后侧被研磨; 将晶片和支撑组合应用于切割粘合带，其具有如此接地的后侧面向切割粘合带，该切割粘合带由切割架围绕并由圆周支撑; 某些外部因素在中间粘合剂层上实现，以降低其粘附力; 并且中间粘合剂层和支撑盘从半导体晶片或芯片移除，而不会损坏半导体晶片或芯片。

5. 发明申请

US20040043616A1 Method for processing a semiconductor wafer including back side grinding 失效
标题翻译：包括背面研磨的半导体晶片的处理方法
公开(公告)号：US20040043616A1
公开(公告)日：2004-03-04
申请号：US10233117
申请日：2002-08-30
发明人： Wesley Harrison , Roland Vandamme , David Gore
IPC分类号： H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L21/02052 , H01L21/02016 , H01L21/02024
摘要： A method is provided for processing the back side of a semiconductor wafer after the wafer has been lapped. The process includes grinding the back side of the wafer to remove wafer material, to substantially eliminate lap damage from the back side of the wafer. The back side of the wafer may then be cleaned, etched, and polished. after which the front side of the wafer is polished. The back side grinding may be accomplished after the lapping without any other step of substantial removal of wafer material. The polishing of the back side of the wafer may be performed with a CMP machine and may produce a specular surface, visually free of damage under haze lamp inspection, with removal of about 0.5 microns of wafer material. After polishing the front side of the wafer, an epitaxial layer may be produced on the front side of the wafer.
摘要翻译：提供了在研磨晶片之后对半导体晶片的背面进行处理的方法。该方法包括研磨晶片的背面以去除晶片材料，以基本上消除从晶片背面的搭接损伤。然后可以清洁，蚀刻和抛光晶片的背面。之后抛光晶片的正面。背面研磨可以在研磨之后完成，而没有任何其他步骤基本上除去晶片材料。可以用CMP机器对晶片的背面进行抛光，并且可以产生镜面，在雾度灯检查下视觉上没有损坏，同时去除约0.5微米的晶片材料。在抛光晶片的前侧之后，可以在晶片的正面上产生外延层。

6. 发明申请

US20030143819A1 Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips 审中-公开
标题翻译：制造具有芯片边缘防护件的半导体芯片的方法，特别是用于晶片级封装芯片的方法
公开(公告)号：US20030143819A1
公开(公告)日：2003-07-31
申请号：US10336373
申请日：2003-01-03
申请人： Infineon Technologies AG
发明人： Harry Hedler , Roland Irsigler , Barbara Vasquez
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50 , H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L23/562 , H01L21/304 , H01L21/3043 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of producing semiconductor chips (1a, 1b, 1c; 1anull, 1bnull, 1cnull) with a protective chip-edge layer (21null, 22null), in particular for wafer level packaging chips, with the steps of: preparing a semiconductor wafer (1); providing trenches (21, 22) in the semiconductor wafer to establish chip edges on a first side of the semiconductor wafer (1); filling the trenches (21, 22) with a protective agent (21null; 22null); grinding back the semiconductor wafer (1) from a second side of the semiconductor wafer (1), which is opposite from the first side, to expose the trenches (21, 22) filled with the protective agent (21null; 22null); and cutting through the trenches (21, 22) filled with the protective agent (21null; 22null), so that the protective chip-edge layer (21null, 22null) comprising the protective agent (21null, 22null) remains on the chip edges.
摘要翻译：本发明提供一种制造具有保护性芯片边缘层（21“，22”）的半导体芯片（1a，1b，1c，1a'，1b'，1c'）的方法，特别是用于晶片级封装芯片具有以下步骤：制备半导体晶片（1）; 在所述半导体晶片中提供沟槽（21,22）以在所述半导体晶片（1）的第一侧上建立芯片边缘; 用保护剂（21'; 22'）填充沟槽（21,22）; 从半导体晶片（1）的与第一侧相反的第二侧研磨半导体晶片（1）以露出填充有保护剂（21'; 22'）的沟槽（21,22）。并切割填充有保护剂（21'; 22'）的沟槽（21,22），使得包含保护剂（21'，22“）的保护性芯片边缘层（21”，22“ ）保留在芯片边缘。

7. 发明申请

US20030134490A1 Method of fabricating semiconductor device on semiconductor wafer 失效
标题翻译：在半导体晶片上制造半导体器件的方法
公开(公告)号：US20030134490A1
公开(公告)日：2003-07-17
申请号：US10263682
申请日：2002-10-04
发明人： Tadashi Inuzuka
IPC分类号： H01L021/30 , H01L021/46 , H01L021/301 , H01L021/78
CPC分类号： H01L21/6836 , H01L21/304 , H01L21/78 , H01L2221/68327
摘要： A method of fabricating a semiconductor device on a semiconductor wafer includes: adhering a carrier plate on an upper surface of the semiconductor wafer via a double-faced protective tape; and thereafter grinding an undersurface of the semiconductor wafer, which includes a circuit pattern formed on the upper surface, to reduce the thickness of the semiconductor wafer.
摘要翻译：在半导体晶片上制造半导体器件的方法包括：通过双面保护带将载体板粘附在半导体晶片的上表面上; 然后研磨包括形成在上表面上的电路图案的半导体晶片的下表面，以减小半导体晶片的厚度。

8. 发明申请

US20030113991A1 Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20030113991A1
公开(公告)日：2003-06-19
申请号：US10307081
申请日：2002-11-27
申请人： Kabushiki Kaisha Shinkawa
发明人： Tooru Maeda
IPC分类号： H01L021/301 , H01L021/46 , H01L021/78 , H01L021/44
CPC分类号： H01L24/12 , H01L21/32051 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/11505 , H01L2224/13099 , H01L2224/45144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A wire bonding method in which conductive patterns that are electrically connected at one end to pads are formed on the surface of a wafer on which a plurality of pads have been formed, and bumps used as connecting points located on the other ends of the conductive patterns are connected to the connecting terminals of a substrate. A disposition of bumps that differs from the disposition of the pads is obtained by the conductive patterns, thus eliminating and adjusting mismatching between the disposition of the pads and the disposition of the connecting terminals.
摘要翻译：在其上形成有多个焊盘的晶片的表面上形成有在一端电连接到焊盘的导电图案的引线接合方法，并且用作连接点的凸点位于导体图案的另一端连接到基板的连接端子。通过导电图案获得不同于焊盘布置的凸块的布置，从而消除和调整焊盘的布置和连接端子的布置之间的不匹配。

9. 发明申请

US20030060024A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20030060024A1
公开(公告)日：2003-03-27
申请号：US10252524
申请日：2002-09-24
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshihisa Imori
IPC分类号： H01L021/46 , H01L021/78 , H01L021/301
CPC分类号： H01L21/6836 , H01L21/3043 , H01L21/78 , H01L2221/68327
摘要： A method of manufacturing a semiconductor device includes non-mechanically forming a groove along a dicing line in a surface of a semiconductor wafer, and cutting the semiconductor wafer along the dicing line to separate the semiconductor wafer into chips.
摘要翻译：制造半导体器件的方法包括在半导体晶片的表面上沿着切割线非机械地形成凹槽，并且沿着切割线切割半导体晶片以将半导体晶片分离成芯片。

10. 发明申请

US20030059979A1 Semiconductor device-manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20030059979A1
公开(公告)日：2003-03-27
申请号：US10253824
申请日：2002-09-25
发明人： Yasunari Ukita , Naotake Watanabe , Ikuo Mori
IPC分类号： H01L021/44 , H01L021/50 , H01L021/48 , H01L021/301 , H01L021/78 , H01L021/46
CPC分类号： H01L23/36 , H01L21/3043 , H01L21/6835 , H01L21/78 , H01L24/45 , H01L24/48 , H01L2221/68377 , H01L2224/1134 , H01L2224/13144 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/00013 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/181 , H01L2224/13099 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor device-manufacturing method includes a laminated wafer formation step and a dicing step. In the laminated wafer formation step, a metal plate is first laid on one side of a wafer with a solder material interposed, and then the metal plate and the wafer are subjected to decompression pressing to form a one-piece structure. As a result, a laminated wafer is obtained. In the dicing step, the laminated wafer is diced into laminated chips.
摘要翻译：半导体器件制造方法包括层叠晶片形成步骤和切割步骤。在层叠晶片形成步骤中，首先将金属板放置在具有焊料材料的晶片的一侧上，然后对金属板和晶片进行减压加压以形成一体式结构。结果，得到层压晶片。在切割步骤中，将层压晶片切割成层叠芯片。

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