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1. 发明申请

US20040266128A1 Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement 审中-公开
标题翻译：具有<100>器件层和<110>衬底的粘合SOI晶片，以提高性能
公开(公告)号：US20040266128A1
公开(公告)日：2004-12-30
申请号：US10894206
申请日：2004-07-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Haur-Ywh Chen , Yi-Ling Chan , Kuo-Nan Yang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L021/76
CPC分类号： H01L21/76251 , Y10S438/977
摘要： A silicon-on-insulator substrate comprises a first silicon substrate having a first crystal orientation, said first substrate having a first polished surface and a first wafer notch; a second silicon substrate having a second crystal orientation different from the first crystal orientation of the first silicon substrate, said second substrate having a second polished surface and a second wafer notch; and the first polished surface of the first silicon substrate being bonded to the second polished surface of the second silicon substrates.
摘要翻译：绝缘体上硅衬底包括具有第一晶体取向的第一硅衬底，所述第一衬底具有第一抛光表面和第一晶片切口; 具有与第一硅衬底的第一晶体取向不同的第二晶体取向的第二硅衬底，所述第二衬底具有第二抛光表面和第二晶片刻蚀; 并且第一硅衬底的第一抛光表面被结合到第二硅衬底的第二抛光表面。

2. 发明申请

US20040266127A1 Method for manufacturing alignment mark of semiconductor device using STI process 失效
标题翻译：使用STI工艺制造半导体器件的对准标记的方法
公开(公告)号：US20040266127A1
公开(公告)日：2004-12-30
申请号：US10737784
申请日：2003-12-18
申请人： Hynix Semiconductor Inc.
发明人： Hyung Hwan Kim
IPC分类号： H01L021/76 , H01L023/544
CPC分类号： H01L23/544 , H01L21/76224 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses method for manufacturing alignment mark wherein a predetermined thickness of a device isolation film is etched prior to removing a pad nitride film during a shallow trench isolation process to increase contrast. In accordance with the method, a pad nitride film pattern and a pad oxide film pattern exposing a predetermined portion of the semiconductor substrate are formed. The semiconductor substrate is etched using the pad nitride film pattern as a mask to form an alignment mark trench. A device isolation film is formed in the trench and a predetermined thickness of the device isolation film is etched to form an alignment mark. The pad nitride film pattern is then removed.
摘要翻译：本发明公开了一种制造对准标记的方法，其中在浅沟槽隔离工艺中在去除衬垫氮化物膜之前对器件隔离膜的预定厚度进行蚀刻以增加对比度。根据该方法，形成露出半导体衬底的预定部分的衬垫氮化物膜图案和衬垫氧化物膜图案。使用衬垫氮化物膜图案作为掩模蚀刻半导体衬底，以形成对准标记沟槽。在沟槽中形成器件隔离膜并蚀刻器件隔离膜的预定厚度以形成对准标记。然后去除衬垫氮化物膜图案。

3. 发明申请

US20040259323A1 Semiconductor structure containing field oxide and method for fabricating the same 审中-公开
标题翻译：含有场氧化物的半导体结构及其制造方法
公开(公告)号：US20040259323A1
公开(公告)日：2004-12-23
申请号：US10024274
申请日：2001-12-17
发明人： Wei-Kang King
IPC分类号： H01L021/76 , H01L029/00
CPC分类号： H01L21/76202
摘要： A semiconductor structure containing a field oxide and a process for fabricating the semiconductor structure. The semiconductor structure includes a semiconductor substrate including an isolation region and an active region; a field oxide formed on the semiconductor substrate in the isolation region; a first pad layer formed on the semiconductor substrate in the active region; a second pad layer formed on the semiconductor substrate not covered by the first pad layer, wherein the second pad layer has a smaller thickness than the first pad layer; a mask layer formed on the first pad layer, wherein the mask layer has a larger width than the first pad layer to form a cavity beneath the mask layer and next to the first pad layer; and a mask filler filled in the cavity. By means of the local pad film thinning technique and by forming a mask filler to grow the field oxide layer, the bird's beak encroachment and the thinning effect of the field oxide layer can both be inhibited.
摘要翻译：包含场氧化物的半导体结构和用于制造半导体结构的工艺。半导体结构包括：半导体衬底，包括隔离区域和有源区域; 形成在隔离区域的半导体衬底上的场氧化物; 在所述有源区中形成在所述半导体衬底上的第一衬垫层; 第二衬垫层，形成在半导体衬底上，未被第一衬垫层覆盖，其中第二衬垫层的厚度小于第一衬垫层; 形成在所述第一焊盘层上的掩模层，其中所述掩模层具有比所述第一焊盘层更大的宽度，以在所述掩模层下面形成并且靠近所述第一焊盘层; 和填充在空腔中的掩模填料。通过局部焊盘薄膜化技术，通过形成掩模填料来生长场氧化物层，可以抑制鸟的喙侵入和场氧化物层的减薄效果。

4. 发明申请

US20040248373A1 Semiconductor devices and methods to form trenches in semiconductor devices 失效
标题翻译：用于在半导体器件中形成沟槽的半导体器件和方法
公开(公告)号：US20040248373A1
公开(公告)日：2004-12-09
申请号：US10746089
申请日：2003-12-26
发明人： Geon-Ook Park
IPC分类号： H01L021/76
CPC分类号： H01L21/76224
摘要： Semiconductor devices and methods of fabricating the same are disclosed. One example method may include forming sequentially a pad oxide film and a silicon nitride film on an entire surface of a semiconductor substrate, forming the trench by etching the silicon nitride film and the semiconductor substrate up to a predetermined depth, and forming a liner oxide film with a thickness thinner than that of the silicon nitride film on an inner wall of the trench. The example method may also include applying a negative voltage to a back surface of the semiconductor substrate and forming an insulation film to fill the trench on the liner oxide film.
摘要翻译：公开了半导体器件及其制造方法。一个示例性方法可以包括在半导体衬底的整个表面上依次形成衬垫氧化物膜和氮化硅膜，通过将氮化硅膜和半导体衬底蚀刻到预定深度来形成沟槽，并形成衬底氧化物膜其厚度比沟槽内壁上的氮化硅膜的厚度薄。示例性方法还可以包括将负电压施加到半导体衬底的背面并形成绝缘膜以填充衬里氧化物膜上的沟槽。

5. 发明申请

US20040235262A1 Silicon-on-nothing fabrication process 失效
标题翻译：无硅制造工艺
公开(公告)号：US20040235262A1
公开(公告)日：2004-11-25
申请号：US10441674
申请日：2003-05-20
申请人： Sharp Laboratories of America, Inc.
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L021/76 , H01L021/00 , H01L021/4763
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/1203 , H01L29/78639 , H01L29/78654
摘要： A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.
摘要翻译：提供了一种在硅衬底上制造无硅器件的方法。公开的无硅无源器件制造在隔离的浮动硅有源区上，因此通过气隙与硅衬底完全隔离。隔离的浮动硅有源区域在具有周围隔离沟槽的硅锗层上制造。然后在选择性地蚀刻硅锗层以形成气隙之前，制造多个锚固件以将硅有源区域锚定到硅衬底。隔离沟填充和平坦化完成隔离浮动硅活性区的形成。隔离浮置硅有源区上的无硅器件可以是多晶硅栅极或金属栅极，并且具有或不具有升高的源极和漏极区域。

6. 发明申请

US20040232488A1 Silicon oxycarbide substrates for bonded silicon on insulator 失效
标题翻译：绝缘体上粘结硅硅碳化硅基板
公开(公告)号：US20040232488A1
公开(公告)日：2004-11-25
申请号：US10443355
申请日：2003-05-21
申请人： Micron Technology, Inc.
发明人： Leonard Forbes
IPC分类号： H01L027/01 , H01L031/0392 , H01L021/76 , H01L029/00
CPC分类号： H01L21/76254
摘要： A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that, it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.
摘要翻译：用于形成绝缘体上半导体结构的方法包括在绝缘基板上形成半导体层，其中基板是与半导体层不同的材料，并且其热膨胀系数基本上等于半导体层的热膨胀系数。半导体层也可以形成为具有这样的厚度，即由于器件加工温度下的温度引起的应变而不能产生。结合到碳硅碳玻璃基板上的硅层提供了绝缘体上硅晶片，其中制造了用于电子器件的电路。

7. 发明申请

US20040218345A1 Products comprising nano-precision engineered electronic components 有权
标题翻译：产品包括纳米精密工程电子元器件
公开(公告)号：US20040218345A1
公开(公告)日：2004-11-04
申请号：US10854446
申请日：2004-05-26
发明人： Tapesh Yadav , Hongxing Hu
IPC分类号： H01L021/76 , H01G009/00 , H01M006/14 , B01J013/00
CPC分类号： B82Y30/00 , B01J12/005 , B01J12/02 , B01J19/24 , B01J2219/00094 , B01J2219/00135 , B01J2219/00155 , B01J2219/00177 , B01J2219/0018 , B01J2219/0894 , B22F1/0003 , B22F9/12 , B22F2999/00 , B29C70/58 , B82B1/00 , B82Y5/00 , B82Y25/00 , C01B13/145 , C01B19/007 , C01B21/062 , C01B32/956 , C01B35/04 , C01F5/06 , C01F11/06 , C01F17/0043 , C01G23/006 , C01G41/02 , C01P2002/01 , C01P2002/02 , C01P2002/34 , C01P2002/54 , C01P2002/60 , C01P2002/72 , C01P2004/03 , C01P2004/04 , C01P2004/38 , C01P2004/51 , C01P2004/54 , C01P2004/61 , C01P2004/62 , C01P2004/64 , C01P2004/82 , C01P2006/10 , C01P2006/12 , C01P2006/40 , C01P2006/60 , C01P2006/80 , C04B2/10 , C04B35/62222 , C04B41/52 , C04B41/89 , C08J5/005 , C08K3/01 , C08K3/08 , C08K2201/011 , H01C7/112 , H01F1/0063 , H01G4/12 , H01G4/33 , H01M4/9066 , H01M8/1213 , H01M8/1246 , H01M8/1253 , Y02E60/525 , Y02P40/42 , Y02P70/56 , Y10S977/89 , Y10T29/49002 , Y10T29/49082 , Y10T428/26 , B22F2202/13 , B22F1/0018
摘要： Electronic devices prepared from nanoscale powders are described. Methods for utilizing nanoscale powders and related nanotechnology to prepare capacitors, inductors, resistors, thermistors, varistors, filters, arrays, interconnects, optical components, batteries, fuel cells, sensors and other products are discussed.
摘要翻译：描述了由纳米级粉末制备的电子器件。讨论了利用纳米级粉末和相关纳米技术制备电容器，电感器，电阻器，热敏电阻器，变阻器，滤波器，阵列，互连，光学部件，电池，燃料电池，传感器和其他产品的方法。

8. 发明申请

US20040198020A1 Local oxidation of silicon (LOCOS) method employing graded oxidation mask 失效
标题翻译：使用梯度氧化掩膜的局部氧化硅（LOCOS）方法
公开(公告)号：US20040198020A1
公开(公告)日：2004-10-07
申请号：US10405708
申请日：2003-04-01
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Chi Lin
IPC分类号： H01L021/76
CPC分类号： H01L21/76202
摘要： A method for forming a local oxidation of silicon (LOCOS) isolation region on a silicon substrate. A series of patterned graded oxidation mask layers formed of a material comprising silicon, oxygen and nitrogen is formed. The series of patterned graded oxidation mask layers has a comparatively high nitrogen:oxygen atomic ratio within a series of first contiguous sub-layers; a comparatively high nitrogen:oxygen atomic ratio within a series of third contiguous sub-layers; and a comparatively low nitrogen:oxygen atomic ratio within a series of second contiguous sub-layers.
摘要翻译：一种用于在硅衬底上形成硅（LOCOS）隔离区域的局部氧化的方法。形成由包含硅，氧和氮的材料形成的一系列图案化的梯度氧化掩模层。一系列图案化梯度氧化掩模层在一系列第一连续子层内具有较高的氮：氧原子比; 在一系列第三连续子层内具有较高的氮：氧原子比; 以及一系列第二连续子层内的相对较低的氮：氧原子比。

9. 发明申请

US20040198019A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20040198019A1
公开(公告)日：2004-10-07
申请号：US10814627
申请日：2004-04-01
申请人： Renesas Technology Corp.
发明人： Kan Yasui , Toshiyuki Mine , Yasushi Goto , Natsuki Yokoyama
IPC分类号： H01L021/76
CPC分类号： H01L21/76224 , Y10S438/907
摘要： In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.
摘要翻译：为了实现根据本发明的隔离沟槽形成方法，其中可以容易地控制氮化硅膜衬垫的结构并且允许器件特征长度的减小和在隔离沟槽中发生的应力的减小，氮化硅膜衬垫首先沉积在形成在硅衬底上的沟槽的内壁上。用于填充沟槽内部的第一嵌入式绝缘体膜的上表面向下凹入以暴露氮化硅膜衬垫的上端部分。接下来，将氮化硅膜衬垫的露出部分转换成诸如氧化硅膜的非氮化硅型绝缘膜。然后将第二嵌入式绝缘膜沉积在第一嵌入式绝缘膜的上部上，然后将沉积的表面平坦化。

10. 发明申请

US20040198017A1 Method to solve alignment mark blinded issues and technology for application of semiconductor etching at a tiny area 有权
标题翻译：解决对准标记盲法问题的方法和在微小区域应用半导体蚀刻技术
公开(公告)号：US20040198017A1
公开(公告)日：2004-10-07
申请号：US10831894
申请日：2004-04-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
发明人： Chung-Long Chang , Henry Lo , Shang-Ting Tsai , Yu-Liang Lin
IPC分类号： H01L021/301 , H01L021/46 , H01L021/76 , H01L021/78
CPC分类号： H01L21/31111 , G03F9/7076 , G03F9/708 , G03F9/7084
摘要： A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.
摘要翻译：一种解开对准标记的方法，包括以下步骤。提供了在对准区域内具有单元区域和对准标记的基板。在沟槽区内形成STI沟槽。在衬底上形成氧化硅层，填充STI沟槽和对准标记。将氧化硅层平坦化以在STI沟槽内形成平坦化的STI，并使对准标记内的氧化硅形成盲目的对准标记。湿法化学蚀刻剂施加在对准标记区域内的盲目对准标记上，以至少部分地去除对准标记内的氧化硅。剩余的氧化硅从盲目的对准标记中移除，以对准对准标记。还公开了一种滴蚀蚀刻装置。

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