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1. 发明申请

US20020185469A1 Method of micromachining a multi-part cavity 失效
标题翻译：微加工多部分腔体的方法
公开(公告)号：US20020185469A1
公开(公告)日：2002-12-12
申请号：US10194167
申请日：2002-07-11
申请人： Applied Materials, Inc.
发明人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
IPC分类号： C23F001/00 , B44C001/22 , C03C015/00 , C03C025/68
CPC分类号： H01L27/1087 , B81B2201/052 , B81B2203/0315 , B81B2203/033 , B81C1/00119 , B81C2201/016 , H01L21/3065 , H01L21/3086
摘要： The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.
摘要翻译：本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

2. 发明申请

US20030189024A1 Etching multi-shaped openings in silicon 失效
标题翻译：在硅中蚀刻多形开口
公开(公告)号：US20030189024A1
公开(公告)日：2003-10-09
申请号：US10118763
申请日：2002-04-08
申请人： Applied Materials Inc.
发明人： Anisul Khan , Sharma V. Pamarthy , Sanjay Thekdi , Ajay Kumar
IPC分类号： C23F001/00
CPC分类号： H01L21/30655
摘要： Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.
摘要翻译：通过交替蚀刻硅中的开口并在侧壁上沉积共形氟碳聚合物来顺序地制备可变形状的开口。该聚合物保护开口的侧壁进一步蚀刻。可以进行各向同性蚀刻以改变蚀刻特征的轮廓，并且用于从硅衬底剥离蚀刻的特征。

3. 发明申请

US20030077878A1 Method for dicing a semiconductor wafer 有权
公开(公告)号：US20030077878A1
公开(公告)日：2003-04-24
申请号：US10035372
申请日：2001-10-19
申请人： Applied Materials, Inc.
发明人： Ajay Kumar , Padmapani C. Nallan , Anisul Khan , Dragan V. Podlesnik
IPC分类号： H01L021/301 , H01L021/46 , H01L021/78
CPC分类号： H01L21/304 , H01L21/78
摘要： A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

4. 发明申请

US20020052113A1 Two etchant etch method 失效
标题翻译：两种蚀刻剂蚀刻方法
公开(公告)号：US20020052113A1
公开(公告)日：2002-05-02
申请号：US10013115
申请日：2001-12-07
申请人： Applied Materials, Inc.
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (nullMEMSnull) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.
摘要翻译：描述了用于蚀刻包括快速和慢刻蚀刻区域的掩模层的两步蚀刻方法。诸如微电机械系统（“MEMS”）应用和混合信号（即模拟和数字）集成电路以及其他集成电路和设备的各种装置中可能会出现快速和慢速的蚀刻区域。在一个实施例中，使用第一蚀刻剂在最快的蚀刻区域中蚀刻穿过该层，然后使用第二蚀刻剂来完成在最慢蚀刻区域中的该层的蚀刻。

5. 发明申请

US20010020516A1 Apparatus for performing self cleaning method of forming deep trenches in silicon substrates 失效
标题翻译：用于在硅衬底中形成深沟槽的自清洁方法的装置
公开(公告)号：US20010020516A1
公开(公告)日：2001-09-13
申请号：US09740146
申请日：2000-12-18
申请人： Applied Materials, Inc.
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L021/3065
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/76232 , H01L27/1087 , Y10S156/916
摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.
摘要翻译：本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

6. 发明申请

US20030176075A1 TECHNIQUES FOR PLASMA ETCHING SILICON-GERMANIUM 失效
标题翻译：等离子体蚀刻硅锗的技术
公开(公告)号：US20030176075A1
公开(公告)日：2003-09-18
申请号：US10093050
申请日：2002-03-06
申请人： Applied Materials, Inc.
发明人： Anisul Khan , Ajay Kumar , Padmapani Nallan
IPC分类号： H01L021/4763
CPC分类号： H01L21/3065 , G02B6/136
摘要： The present invention provides novel etching techniques for etching SinullGe, employing SF6/fluorocarbon etch chemistries at a low bias power. These plasma conditions are highly selective to organic photoresist. The techniques of the present invention are suitable for fabricating optically smooth SinullGe surfaces. A cavity was etched in a layer of a first SinullGe composition using SF6/C4F8 etch chemistry at low bias power. The cavity was then filled with a second SinullGe composition having a higher refractive index than the first SinullGe composition. A waveguide was subsequently fabricated by depositing a cladding layer on the second SinullGe composition that was formed in the cavity. In a further embodiment a cluster tool is employed for executing processing steps of the present invention inside the vacuum environment of the cluster tool. In an additional embodiment a manufacturing system is provided for fabricating waveguides of the present invention. The manufacturing system includes a controller that is adapted for interacting with a plurality of fabricating stations.
摘要翻译：本发明提供了用于蚀刻Si-Ge的新颖蚀刻技术，其采用SF6 /氟碳蚀刻化学品，以低偏压功率。这些等离子体条件对有机光致抗蚀剂具有高选择性。本发明的技术适用于制造光学平滑的Si-Ge表面。在低偏压功率下，使用SF6 / C4F8蚀刻化学法在第一Si-Ge组合物的层中蚀刻空腔。然后用具有比第一Si-Ge组合物更高的折射率的第二Si-Ge组合物填充空腔。随后通过在形成在空腔中的第二Si-Ge组合物上沉积包覆层来制造波导。在另一个实施例中，采用集群工具来在集群工具的真空环境内执行本发明的处理步骤。在另外的实施例中，提供制造系统用于制造本发明的波导。该制造系统包括适于与多个制造站相互作用的控制器。

7. 发明申请

US20010051439A1 Self cleaning method of forming deep trenches in silicon substrates 审中-公开
公开(公告)号：US20010051439A1
公开(公告)日：2001-12-13
申请号：US09864705
申请日：2001-05-23
申请人： Applied Materials, Inc.
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L021/302
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/76232 , H01L27/1087 , Y10S156/916
摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

8. 发明申请

US20010019897A1 High etch rate method for plasma etching silicon nitride 失效
标题翻译：用于等离子体蚀刻氮化硅的高蚀刻速率方法
公开(公告)号：US20010019897A1
公开(公告)日：2001-09-06
申请号：US09853847
申请日：2001-05-11
申请人： Applied Materials, Inc.
发明人： Ajay Kumar , Anisul Khan , Jeffrey D. Chinn , Dragan V. Podlesnik
IPC分类号： H01L021/302 , C23F003/00 , H01L021/461 , C23F001/02
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32935 , H01L21/3065
摘要： This invention is directed to a method for plasma etching difficult to etch materials at a high etch rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes a plasma formed by energy provided from two separate power sources and a gaseous mixture that includes only an etchant gas and a sputtering gas. The power levels from the separate power sources and the ratio between the flow rates of the etchant gas and a sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched the. In the second step, a low etch rate process having an etch rate below about two microns per minute is used remove any residual material not removed by the first etch step.
摘要翻译：本发明涉及一种用于等离子体蚀刻的方法，其难以以高蚀刻速率蚀刻材料。该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。该方法包括通过由两个单独的电源提供的能量形成的等离子体和仅包括蚀刻剂气体和溅射气体的气体混合物。可以有利地调节来自分离的电源的功率水平以及蚀刻剂气体和溅射气体的流量之间的比率，以获得大于每分钟2微米的氮化硅的蚀刻速率。另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。两步法的第一蚀刻步骤提供了大约每分钟2微米的高蚀刻速率，以便基本上去除所有待蚀刻的层。在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺去除通过第一蚀刻步骤未被去除的任何残留材料。

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