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91. 发明授权

US08127081B2 Memory hub and access method having internal prefetch buffers 有权
标题翻译：具有内部预取缓冲区的内存集线器和访问方法
公开(公告)号：US08127081B2
公开(公告)日：2012-02-28
申请号：US12185615
申请日：2008-08-04
申请人： Terry R. Lee , Joseph Jeddeloh
发明人： Terry R. Lee , Joseph Jeddeloh
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024 , G06F2212/6026
摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
摘要翻译：存储器模块包括耦合到多个存储器件的存储器集线器。存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。标签逻辑存储与预取数据的地址对应的预取地址。标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。如果是，则从预取缓冲器读取所请求的数据。否则，从存储器件读取所请求的数据。

92. 发明申请

US20120039123A1 MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件中的多级编程
公开(公告)号：US20120039123A1
公开(公告)日：2012-02-16
申请号：US13279717
申请日：2011-10-24
申请人： Hagop A. Nazarian
发明人： Hagop A. Nazarian
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C2211/5648
摘要： The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.
摘要翻译：本发明的编程方法通过在具有最高阈值电压的逻辑状态的同一字线上最初编程单元来最小化程序干扰。字线上的剩余单元按照降低阈值电压电平的顺序被编程到它们各自的逻辑状态。

93. 发明申请

US20120033513A1 DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES 失效
标题翻译：分布式写入数据驱动器，用于冲突访问记忆
公开(公告)号：US20120033513A1
公开(公告)日：2012-02-09
申请号：US13275568
申请日：2011-10-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C8/18
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读命令每次突发存取发出一次，消除了周期频率下的切换读控制线。控制线转换终止访问并初始化另一个突发访问。

94. 发明授权

US08107304B2 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US08107304B2
公开(公告)日：2012-01-31
申请号：US12642414
申请日：2009-12-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。控制线转换终止访问并初始化另一个突发访问。写周期时间最大化，从而允许突发模式工作频率的增加。读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

95. 发明授权

US08098508B2 Configurable inputs and outputs for memory stacking system and method 有权
标题翻译：用于内存堆叠系统和方法的可配置输入和输出
公开(公告)号：US08098508B2
公开(公告)日：2012-01-17
申请号：US12559373
申请日：2009-09-14
申请人： Jeffery W Janzen
发明人： Jeffery W Janzen
IPC分类号： G11C5/06
CPC分类号： G11C7/1078 , G11C5/02 , G11C5/04 , G11C7/109 , G11C7/22 , G11C7/225 , G11C11/4093 , G11C11/4096 , G11C2207/2254 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01055
摘要： Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.
摘要翻译：本发明的实施例涉及用于存储器和存储器堆叠应用的可配置输入和/或输出。更具体地，本发明的实施例包括存储器件，其包括具有配置为通过特定信号实现的电路的管芯，被配置为接收特定信号的输入引脚，以及路径选择器，其被配置为选择性地指定到电路的信号路径从输入引脚。

96. 发明申请

US20120002474A1 INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM 有权
标题翻译：独立的内存程序和验证方法，设备和系统
公开(公告)号：US20120002474A1
公开(公告)日：2012-01-05
申请号：US13206019
申请日：2011-08-09
申请人： Daniel H. Doyle
发明人： Daniel H. Doyle
IPC分类号： G11C16/02
CPC分类号： G11C7/1042 , G11C16/10 , G11C16/3454 , G11C16/3481 , G11C2216/22
摘要： An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.
摘要翻译：交织的存储器编程和验证方法，设备和系统包括包括存储器单元的第一和第二存储器组的存储器阵列。存储器件还包括控制器，该控制器被配置为使用第一和第二存储器库中的每一个中的迭代编程和验证操作，将第一数据同时编程到第一存储器组中，并且将第二数据转换为第二存储器组，其中编程和验证操作在第二存储体与第一存储体中的编程和验证操作相抵消。

97. 发明申请

US20110307649A1 MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK 失效
标题翻译：具有单位单元的多级单元存储器件，可重新映射的存储器块
公开(公告)号：US20110307649A1
公开(公告)日：2011-12-15
申请号：US13213538
申请日：2011-08-19
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G06F12/02
CPC分类号： G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C29/76 , G11C2211/5641
摘要： A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.
摘要翻译：具有非易失性存储器件的系统具有被组织到存储块中的多个存储器单元。块可以以每个单元模式的多位操作或每单元模式的单个位操作。处理器控制系统并选择块以每单元模式的多位操作和每单元模式的单位操作。一个专用存储块只能在每个单元模式的单个位中运行。如果发现专用存储器块是有缺陷的，则无缺陷块可以被重新映射到该专用存储器块位置，以仅在每个单元模式的单个位中起作用。

98. 发明申请

US20110273297A1 METHOD AND SYSTEM FOR IDENTIFYING MISSING ITEMS 失效
标题翻译：识别缺陷项的方法和系统
公开(公告)号：US20110273297A1
公开(公告)日：2011-11-10
申请号：US13184952
申请日：2011-07-18
申请人： Dennis D. Elledge
发明人： Dennis D. Elledge
IPC分类号： G08B13/14
CPC分类号： G08B13/2462 , G06F21/88 , G06K7/0008 , G06K7/10059 , G06K7/10356 , G06K2017/0077 , G06Q10/087 , G08B13/14 , G08B13/2402 , G08B13/2417 , G08B21/0275 , G08B21/24
摘要： A system for identifying a lost or stolen device includes a transmitter, a receiver and a computer. The transmitter is coupled to the device and transmits identification information. The receiver receives the identification information transmitted by the transmitter when the transmitter is within a defined distance from the receiver. The computer is coupled to the receiver so as to receive the information from the receiver. The computer has a first secure database which stores data associated with lost or stolen devices and which prevents unauthorized access to the data stored therein. The computer compares the information with the stored data, and generates an alarm if the information matches at least some of the stored data.
摘要翻译：用于识别丢失或被盗设备的系统包括发射机，接收机和计算机。发射机耦合到设备并发送识别信息。当发射机距离接收机一定距离内时，接收机接收发射机发送的识别信息。计算机耦合到接收器，以便从接收器接收信息。计算机具有第一安全数据库，其存储与丢失或被盗设备相关联的数据，并且防止未经授权的访问存储在其中的数据。计算机将信息与存储的数据进行比较，并且如果信息与至少一些所存储的数据匹配，则生成报警。

99. 发明授权

US08054362B2 Increasing readout speed in CMOS APS sensors through block readout 有权
标题翻译：通过块读出增加CMOS APS传感器的读出速度
公开(公告)号：US08054362B2
公开(公告)日：2011-11-08
申请号：US12571460
申请日：2009-10-01
申请人： Lin-Ping Ang
发明人： Lin-Ping Ang
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/378 , H04N5/23241
摘要： A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.
摘要翻译：一种方法和相关联的架构，用于以减少读出线上的寄生电容的方式分离有源像素传感器中的列读出电路。在优选实施例中，列读出电路被分组成块并且具有块信令。因此，所选块中只有列输出电路显着地赋予共享列读出线上的寄生电容效应。块信号允许增加像素读出速率，同时保持恒定的帧速率用于大尺寸高速成像应用。

100. 发明授权

US08054361B2 Increasing readout speed in CMOS aps sensors through block readout 有权
标题翻译：通过块读数增加CMOS aps传感器的读出速度
公开(公告)号：US08054361B2
公开(公告)日：2011-11-08
申请号：US12566814
申请日：2009-09-25
申请人： Lin-Ping Ang
发明人： Lin-Ping Ang
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/378 , H04N5/23241
摘要： A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.
摘要翻译：一种方法和相关联的架构，用于以减少读出线上的寄生电容的方式分离有源像素传感器中的列读出电路。在优选实施例中，列读出电路被分组成块并且具有块信令。因此，所选块中只有列输出电路显着地赋予共享列读出线上的寄生电容效应。块信号允许增加像素读出速率，同时保持恒定的帧速率用于大尺寸高速成像应用。

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