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1. 发明授权

US06728142B2 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US06728142B2
公开(公告)日：2004-04-27
申请号：US10231942
申请日：2002-08-29
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C800
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
摘要翻译：集成电路存储器件被设计为执行高速数据写入周期。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。写周期时间最大化以允许突发模式工作频率的增加。阵列读出放大器附近的局部逻辑门用于控制写入数据驱动器，以提供最大的写入时间，而不会在输入/输出线路平衡周期期间交叉电流。通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

2. 发明授权

US5852371A Low power, high speed level shifter 失效
公开(公告)号：US5852371A
公开(公告)日：1998-12-22
申请号：US890921
申请日：1997-07-10
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： H03K19/0185 , G11C11/407 , H03K3/356 , H03K19/0948
CPC分类号： H03K3/356017 , H03K3/356113
摘要： A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.

3. 发明授权

US08213244B2 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写数据驱动程序
公开(公告)号：US08213244B2
公开(公告)日：2012-07-03
申请号：US13275568
申请日：2011-10-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读命令每次突发存取发出一次，消除了周期频率下的切换读控制线。控制线转换终止访问并初始化另一个突发访问。

4. 发明申请

US20100097868A1 DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES 失效
标题翻译：分布式写入数据驱动器，用于冲突访问记忆
公开(公告)号：US20100097868A1
公开(公告)日：2010-04-22
申请号：US12642414
申请日：2009-12-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。控制线转换终止访问并初始化另一个突发访问。写周期时间最大化，从而允许突发模式工作频率的增加。读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

5. 发明授权

US07160795B2 Method and structures for reduced parasitic capacitance in integrated circuit metallizations 有权
标题翻译：集成电路金属化中减小寄生电容的方法和结构
公开(公告)号：US07160795B2
公开(公告)日：2007-01-09
申请号：US10293789
申请日：2002-11-12
申请人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
发明人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

6. 发明授权

US06381180B1 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US06381180B1
公开(公告)日：2002-04-30
申请号：US09031325
申请日：1998-02-26
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C11401
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency.. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
摘要翻译：集成电路存储器件被设计为执行高速数据写入周期。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每突发存取发出一次，无需在器件周期频率下切换读/写控制线。在突发存取期间，读/写控制线的转换用于终止突发存取并初始化该设备用于另一个突发存取。写周期时间最大化以允许突发模式工作频率的增加。阵列读出放大器附近的局部逻辑门用于控制写入数据驱动器，以提供最大的写入时间，而不会在输入/输出线路平衡周期内交叉电流。通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

7. 发明授权

US5745429A Memory having and method for providing a reduced access time 失效
标题翻译：存储器和提供减少的存取时间的方法
公开(公告)号：US5745429A
公开(公告)日：1998-04-28
申请号：US520241
申请日：1995-08-28
申请人： Timothy B. Cowles , Troy A. Manning , Todd A. Merritt
发明人： Timothy B. Cowles , Troy A. Manning , Todd A. Merritt
IPC分类号： G11C8/06 , G11C8/18 , G11C8/00
CPC分类号： G11C8/18 , G11C8/06
摘要： A memory device includes an array of memory cells that are arranged in row and columns. A row latch receives a row address and a latch signal and stores the row address in response to a transition of the latch signal. A row decoder is coupled between the latch and the array. In response to a transition of a row address strobe, which occurs a first predetermined time after the transition of the latch signal, the row decoder fires a row of the memory cells that are identified by the row address.
摘要翻译：存储器件包括排列成行和列的存储器单元阵列。行锁存器接收行地址和锁存信号，并且响应于锁存信号的转变而存储行地址。行解码器耦合在锁存器和阵列之间。响应于在锁存信号转换之后的第一预定时间发生的行地址选通器的转变，行解码器触发由行地址识别的一行存储器单元。

8. 发明授权

US5598376A Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US5598376A
公开(公告)日：1997-01-28
申请号：US497354
申请日：1995-06-30
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C11/401 , G06F12/06 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C7/22 , G06F2212/2022
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
摘要翻译：集成电路存储器件被设计为执行高速数据写入周期。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。写周期时间最大化以允许突发模式工作频率的增加。阵列读出放大器附近的局部逻辑门用于控制写入数据驱动器，以提供最大的写入时间，而不会在输入/输出线路平衡周期期间交叉电流。通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

9. 发明授权

US07646654B2 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US07646654B2
公开(公告)日：2010-01-12
申请号：US12144446
申请日：2008-06-23
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。控制线转换终止访问并初始化另一个突发访问。写周期时间最大化，从而允许突发模式工作频率的增加。读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

10. 发明授权

US07397711B2 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US07397711B2
公开(公告)日：2008-07-08
申请号：US11419166
申请日：2006-05-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。控制线转换终止访问并初始化另一个突发访问。写周期时间最大化，从而允许突发模式工作频率的增加。读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

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