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1. 发明授权

US08127081B2 Memory hub and access method having internal prefetch buffers 有权
标题翻译：具有内部预取缓冲区的内存集线器和访问方法
公开(公告)号：US08127081B2
公开(公告)日：2012-02-28
申请号：US12185615
申请日：2008-08-04
申请人： Terry R. Lee , Joseph Jeddeloh
发明人： Terry R. Lee , Joseph Jeddeloh
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024 , G06F2212/6026
摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
摘要翻译：存储器模块包括耦合到多个存储器件的存储器集线器。存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。标签逻辑存储与预取数据的地址对应的预取地址。标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。如果是，则从预取缓冲器读取所请求的数据。否则，从存储器件读取所请求的数据。

2. 发明申请

US20090187714A1 MEMORY HUB AND ACCESS METHOD HAVING INTERNAL PREFETCH BUFFERS 有权
标题翻译：具有内部预留缓冲区的存储器和访问方法
公开(公告)号：US20090187714A1
公开(公告)日：2009-07-23
申请号：US12185615
申请日：2008-08-04
申请人： Terry R. Lee , Joseph Jeddeloh
发明人： Terry R. Lee , Joseph Jeddeloh
IPC分类号： G06F12/02 , G06F15/16
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024 , G06F2212/6026
摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
摘要翻译：存储器模块包括耦合到多个存储器件的存储器集线器。存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。标签逻辑存储与预取数据的地址对应的预取地址。标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。如果是，则从预取缓冲器读取所请求的数据。否则，从存储器件读取所请求的数据。

3. 发明授权

US07260685B2 Memory hub and access method having internal prefetch buffers 有权
标题翻译：具有内部预取缓冲区的内存集线器和访问方法
公开(公告)号：US07260685B2
公开(公告)日：2007-08-21
申请号：US10601252
申请日：2003-06-20
申请人： Terry R. Lee , Joseph Jeddeloh
发明人： Terry R. Lee , Joseph Jeddeloh
IPC分类号： G06F12/06
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024 , G06F2212/6026
摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
摘要翻译：存储器模块包括耦合到多个存储器件的存储器集线器。存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。标签逻辑存储与预取数据的地址对应的预取地址。标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。如果是，则从预取缓冲器读取所请求的数据。否则，从存储器件读取所请求的数据。

4. 发明申请

US20080098253A1 Method of timing calibration using slower data rate pattern 有权
公开(公告)号：US20080098253A1
公开(公告)日：2008-04-24
申请号：US12000434
申请日：2007-12-12
申请人： Terry Lee , Kevin Ryan , Joseph Jeddeloh
发明人： Terry Lee , Kevin Ryan , Joseph Jeddeloh
IPC分类号： G06F1/08
CPC分类号： G01R31/31937 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2254 , H03L7/0812 , H03L7/0814
摘要： An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

5. 发明申请

US20070101075A1 Out of order DRAM sequencer 有权
标题翻译：乱序DRAM音序器
公开(公告)号：US20070101075A1
公开(公告)日：2007-05-03
申请号：US11604906
申请日：2006-11-28
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0676 , G06F12/14 , G06F13/1626 , G06F2003/0691
摘要： Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requesters in the order in which the read requests were originally received.
摘要翻译：存储器访问请求被连续地接收在存储器控制器的存储器请求队列中。检测到如果以接收到的顺序执行存储器访问请求将发生的临时邻近请求之间的任何冲突或潜在的延迟，并且重新排列接收的存储器访问请求的顺序以避免或最小化冲突或延迟并优化数据流向和从存储器数据总线流出。在重新排序的序列中执行存储器访问请求，同时跟踪请求的原始接收顺序。在执行之后，通过执行读取型存储器访问请求从存储器件读取的数据按照最初接收读取请求的顺序被传送到各个请求者。

6. 发明申请

US20070011392A1 Reconfigurable memory module and method 有权
标题翻译：可重构内存模块和方法
公开(公告)号：US20070011392A1
公开(公告)日：2007-01-11
申请号：US11522175
申请日：2006-09-15
申请人： Terry Lee , Joseph Jeddeloh
发明人： Terry Lee , Joseph Jeddeloh
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F12/0661 , G06F13/1694 , G06F13/4239
摘要： A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
摘要翻译：计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。

7. 发明申请

US20060179208A1 System and method for memory hub-based expansion bus 有权
公开(公告)号：US20060179208A1
公开(公告)日：2006-08-10
申请号：US11399873
申请日：2006-04-07
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/14
CPC分类号： G06F13/4022 , G06F13/4234 , G06F13/4247 , Y10S370/912
摘要： A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

8. 发明申请

US20060047887A1 Memory system and method having unidirectional data buses 有权
标题翻译：具有单向数据总线的存储器系统和方法
公开(公告)号：US20060047887A1
公开(公告)日：2006-03-02
申请号：US10928411
申请日：2004-08-27
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/14
CPC分类号： G11C7/1072 , G06F13/4243
摘要： A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.
摘要翻译：存储器系统和方法包括将来自存储器控制器的写入数据耦合到多个存储器件的单向下游总线，以及单向上游总线将从存储器件读取的数据耦合到存储器控制器。存储器件各自包括用于存储写入数据的写入缓冲器，直到相应的存储器件不再忙于处理读取存储器请求。下游总线也可以用于将存储器命令和/或行和列地址从存储器控制器耦合到存储器件。

9. 发明申请

US20050050255A1 Multiple processor system and method including multiple memory hub modules 有权
标题翻译：多处理器系统和方法包括多个内存集线器模块
公开(公告)号：US20050050255A1
公开(公告)日：2005-03-03
申请号：US10653044
申请日：2003-08-28
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F20060101 , G06F13/00 , G11C5/00
CPC分类号： G11C5/00 , G06F12/0862 , G06F13/4022
摘要： A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.
摘要翻译：基于处理器的电子系统包括布置在第一和第二等级中的几个存储器模块。第一级的存储器模块由几个处理器中的任何一个直接访问，并且第二级的存储器模块由处理器通过第一级的存储器模块访问。通过改变用于访问第二组中的存储器模块的第一级中的存储器模块的数量来改变处理器和第二级中的存储器模块之间的数据带宽。每个存储器模块包括耦合到存储器集线器的多个存储器件。存储器集线器包括耦合到每个存储器设备的存储器控制器，耦合到相应处理器或存储器模块的链路接口以及将任何存储器控制器耦合到任何链路接口的交叉开关。

10. 发明授权

US06636946B2 System and method for caching data based on identity of requestor 有权
公开(公告)号：US06636946B2
公开(公告)日：2003-10-21
申请号：US09805663
申请日：2001-03-13
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F1200
CPC分类号： G06F12/0888
摘要： In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.

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