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1. 发明申请

US20080098253A1 Method of timing calibration using slower data rate pattern 有权
公开(公告)号：US20080098253A1
公开(公告)日：2008-04-24
申请号：US12000434
申请日：2007-12-12
申请人： Terry Lee , Kevin Ryan , Joseph Jeddeloh
发明人： Terry Lee , Kevin Ryan , Joseph Jeddeloh
IPC分类号： G06F1/08
CPC分类号： G01R31/31937 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2254 , H03L7/0812 , H03L7/0814
摘要： An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

2. 发明申请

US20070101075A1 Out of order DRAM sequencer 有权
标题翻译：乱序DRAM音序器
公开(公告)号：US20070101075A1
公开(公告)日：2007-05-03
申请号：US11604906
申请日：2006-11-28
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0676 , G06F12/14 , G06F13/1626 , G06F2003/0691
摘要： Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requesters in the order in which the read requests were originally received.
摘要翻译：存储器访问请求被连续地接收在存储器控制器的存储器请求队列中。检测到如果以接收到的顺序执行存储器访问请求将发生的临时邻近请求之间的任何冲突或潜在的延迟，并且重新排列接收的存储器访问请求的顺序以避免或最小化冲突或延迟并优化数据流向和从存储器数据总线流出。在重新排序的序列中执行存储器访问请求，同时跟踪请求的原始接收顺序。在执行之后，通过执行读取型存储器访问请求从存储器件读取的数据按照最初接收读取请求的顺序被传送到各个请求者。

3. 发明申请

US20070011392A1 Reconfigurable memory module and method 有权
标题翻译：可重构内存模块和方法
公开(公告)号：US20070011392A1
公开(公告)日：2007-01-11
申请号：US11522175
申请日：2006-09-15
申请人： Terry Lee , Joseph Jeddeloh
发明人： Terry Lee , Joseph Jeddeloh
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F12/0661 , G06F13/1694 , G06F13/4239
摘要： A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
摘要翻译：计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。

4. 发明申请

US20060179208A1 System and method for memory hub-based expansion bus 有权
公开(公告)号：US20060179208A1
公开(公告)日：2006-08-10
申请号：US11399873
申请日：2006-04-07
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/14
CPC分类号： G06F13/4022 , G06F13/4234 , G06F13/4247 , Y10S370/912
摘要： A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

5. 发明申请

US20060047887A1 Memory system and method having unidirectional data buses 有权
标题翻译：具有单向数据总线的存储器系统和方法
公开(公告)号：US20060047887A1
公开(公告)日：2006-03-02
申请号：US10928411
申请日：2004-08-27
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F12/14
CPC分类号： G11C7/1072 , G06F13/4243
摘要： A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.
摘要翻译：存储器系统和方法包括将来自存储器控制器的写入数据耦合到多个存储器件的单向下游总线，以及单向上游总线将从存储器件读取的数据耦合到存储器控制器。存储器件各自包括用于存储写入数据的写入缓冲器，直到相应的存储器件不再忙于处理读取存储器请求。下游总线也可以用于将存储器命令和/或行和列地址从存储器控制器耦合到存储器件。

6. 发明申请

US20050050255A1 Multiple processor system and method including multiple memory hub modules 有权
标题翻译：多处理器系统和方法包括多个内存集线器模块
公开(公告)号：US20050050255A1
公开(公告)日：2005-03-03
申请号：US10653044
申请日：2003-08-28
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F20060101 , G06F13/00 , G11C5/00
CPC分类号： G11C5/00 , G06F12/0862 , G06F13/4022
摘要： A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.
摘要翻译：基于处理器的电子系统包括布置在第一和第二等级中的几个存储器模块。第一级的存储器模块由几个处理器中的任何一个直接访问，并且第二级的存储器模块由处理器通过第一级的存储器模块访问。通过改变用于访问第二组中的存储器模块的第一级中的存储器模块的数量来改变处理器和第二级中的存储器模块之间的数据带宽。每个存储器模块包括耦合到存储器集线器的多个存储器件。存储器集线器包括耦合到每个存储器设备的存储器控制器，耦合到相应处理器或存储器模块的链路接口以及将任何存储器控制器耦合到任何链路接口的交叉开关。

7. 发明授权

US06636946B2 System and method for caching data based on identity of requestor 有权
公开(公告)号：US06636946B2
公开(公告)日：2003-10-21
申请号：US09805663
申请日：2001-03-13
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F1200
CPC分类号： G06F12/0888
摘要： In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.

8. 发明授权

US06385680B1 Method for flexibly allocating request/grant pins between multiple bus controllers 有权
标题翻译：在多总线控制器之间灵活分配请求/授权引脚的方法
公开(公告)号：US06385680B1
公开(公告)日：2002-05-07
申请号：US09418468
申请日：1999-10-15
申请人： Douglas A. Larson , Joseph Jeddeloh , Jeffrey J. Rooney
发明人： Douglas A. Larson , Joseph Jeddeloh , Jeffrey J. Rooney
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the first set of output pins, and during a second mode of operation the third subset of grant lines is selected to driven through the first set of output pins.
摘要翻译：本发明的一个实施例提供一种用于在位于半导体芯片上的总线控制器之间灵活地分配用于总线授权信号的I / O引脚的方法。该方法通过从第一总线仲裁电路接收第一组授权线来操作。第一组授权线路用于将第一总线的控制权授予第一总线上的设备。该方法将第一组授权线划分为授权线的第一子集和授权线的第二子集。该方法还从第二总线仲裁电路接收第二组授权线路。第二组授权线用于将第二总线的控制权授予第二总线上的设备。该方法将第二组授权线划分为授权线的第三子集和授权线的第四子集。接下来，该方法从授权线的第一子集和授权线的第三子集之间选择输出，并通过第一组输出引脚将输出驱动出半导体芯片。在第一操作模式期间，授权线路的第一子集被选择为通过第一组输出引脚驱动，并且在第二操作模式期间，授权线路的第三子集被选择为通过第一组输出引脚。

9. 发明授权

US06252612B1 Accelerated graphics port for multiple memory controller computer system 失效
标题翻译：用于多个内存控制器计算机系统的加速图形端口
公开(公告)号：US06252612B1
公开(公告)日：2001-06-26
申请号：US09000511
申请日：1997-12-30
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F1316
CPC分类号： G09G5/363 , G06F12/0292 , G06F12/1081 , G09G5/39
摘要： An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.
摘要翻译：用于从多个存储器控制器之一存储，寻址和检索图形数据的架构。在本发明的第一实施例中，具有加速图形端口（AGP）的存储器控制器之一包括定义由存储器控制器处理的优选地用于所有AGP事务的地址范围的一组寄存器。 AGP使用图形地址重映射表（GART）来映射内存。 GART包括具有翻译信息的页表条目，以将落在GART范围内的虚拟地址重新映射到其对应的物理地址。在本发明的第二实施例中，多个存储器控制器具有AGP，其中多个存储器控制器中的每一个提供一组定义优选用于AGP事务的地址范围的寄存器。在本发明的第三实施例中，在单个芯片上实现的多个存储器控制器各自包含AGP和一组配置寄存器，用于标识优选用于AGP事务的地址范围。

10. 发明授权

US6085339A System for memory error handling 有权
标题翻译：内存错误处理系统
公开(公告)号：US6085339A
公开(公告)日：2000-07-04
申请号：US201277
申请日：1998-11-30
申请人： Joseph Jeddeloh
发明人： Joseph Jeddeloh
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1024 , G06F11/1048 , G06F11/1056
摘要： A computer system stores data according to a plurality of different error handling schemes. The computer system includes a memory controller with a plurality of different error handling modules, each of which can be selectively associated with one or more memory blocks. Each of the error handling modules is structured to write data to and read data from its associated memory block according to a different error handling scheme. A memory controller includes a separate configuration register for each of the plurality of memory blocks. Each configuration register stores an indication of the error handling module that will be employed to write data to and read data from the memory block associated with the configuration register.
摘要翻译：计算机系统根据多种不同的错误处理方案存储数据。计算机系统包括具有多个不同错误处理模块的存储器控制器，每个错误处理模块可以选择性地与一个或多个存储块相关联。每个错误处理模块被构造成根据不同的错误处理方案向相关联的存储器块写入数据并从其读取数据。存储器控制器包括用于多个存储器块中的每一个的独立配置寄存器。每个配置寄存器存储将用于向与配置寄存器相关联的存储器块写入数据和从其读取数据的错误处理模块的指示。

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