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91. 发明授权

US06483156B1 Double planar gated SOI MOSFET structure 失效
标题翻译：双平面门控SOI MOSFET结构
公开(公告)号：US06483156B1
公开(公告)日：2002-11-19
申请号：US09526857
申请日：2000-03-16
申请人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
发明人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66795
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.
摘要翻译：通过使用心轴浅沟槽隔离形成工艺制造双门控绝缘体上硅（SOI）MOSFET，随后是镶嵌栅极。双门控MOSFET具有狭窄的扩散线，其通过光刻或光刻和缩小限定，由STI样心轴工艺限定的镶嵌工艺。双门控SOI MOSFET增加每个布局宽度的电流驱动，并提供低导通电流。

92. 发明授权

US06433372B1 Dense multi-gated device design 失效
标题翻译：密集的多门控设备设计
公开(公告)号：US06433372B1
公开(公告)日：2002-08-13
申请号：US09527863
申请日：2000-03-17
申请人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
发明人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H01L2972
CPC分类号： H01L29/66484
摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.
摘要翻译：具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。

93. 发明授权

US06426278B1 Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos 失效
标题翻译：投影气体浸没激光掺杂工艺（PGILD）制造扩散光晕
公开(公告)号：US06426278B1
公开(公告)日：2002-07-30
申请号：US09413997
申请日：1999-10-07
申请人： Edward J. Nowak , John J. Ellis-Monaghan
发明人： Edward J. Nowak , John J. Ellis-Monaghan
IPC分类号： H01L21425
CPC分类号： H01L21/26513 , H01L21/223 , H01L21/26506 , H01L21/268 , H01L29/6656 , H01L29/6659
摘要： A method for fabricating FETs with abrupt halos provides an initial FET structure having a substrate, a dielectric layer over a portion of the substrate, a gate over the dielectric layer, sidewall insulators on either side of and adjacent the dielectric layer and gate, and halo regions comprising an n- or p-type dopant extending to a desired depth in the substrate adjacent each of the sidewall insulators and beneath a portion of the dielectric layer. The method is practiced by creating first amorphous regions within a portion of each of the halo regions to a depth less than the halo regions and implanting in and diffusing throughout only the first amorphous regions a dopant opposite the n- or p-type dopant used in the halo region to create extension source and drain regions. The method then involves forming dielectric spacers adjacent the sidewall insulators and creating second amorphous regions adjacent each of the dielectric spacers to a depth greater than the halo regions. Thereafter, there is implanted in and diffused throughout only the second amorphous regions a dopant opposite the n- or p-type dopant used in the halo region to create source and drain regions. The diffusion of dopant may be by laser annealing to locally melt only the amorphous region.
摘要翻译：用于制造具有突变光晕的FET的方法提供了初始FET结构，其具有衬底，在衬底的一部分上的电介质层，介电层上的栅极，介电层和栅极两侧和邻近电介质层和栅极的侧壁绝缘体，以及卤素包括n型或p型掺杂物的区域，其延伸到邻近每个侧壁绝缘体的衬底中的所需深度并且在电介质层的一部分之下。该方法通过在每个晕圈区域的一部分内形成第一非晶区域到达小于卤素区域的深度来实现，并且仅在第一非晶区域内植入和扩散与n型或p型掺杂剂相反的掺杂剂卤素区域产生扩展源极和漏极区域。该方法然后涉及形成邻近侧壁绝缘体的介电间隔物，并产生与每个电介质间隔物相邻的第二非晶区域至大于卤素区域的深度。此后，仅在第二非晶区域中注入并扩散与在晕区域中使用的n型或p型掺杂剂相反的掺杂剂以产生源区和漏区。掺杂剂的扩散可以通过激光退火以局部仅熔融无定形区域。

94. 发明授权

US6096584A Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region 失效
标题翻译：绝缘体上硅和CMOS-on-SOI双膜制造工艺，具有共面的硅和隔离层，并在一个区域上添加第二硅层
公开(公告)号：US6096584A
公开(公告)日：2000-08-01
申请号：US38936
申请日：1998-03-12
申请人： John J. Ellis-Monaghan , Steven H. Voldman
发明人： John J. Ellis-Monaghan , Steven H. Voldman
IPC分类号： H01L27/04 , H01L21/822 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/786 , H01L21/00
CPC分类号： H01L27/0251 , H01L21/84 , H01L27/1203
摘要： Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.
摘要翻译：在制造所选择的电子部件（包括电阻器，电容器和二极管）期间，在硅绝缘体（SOI）衬底上的选定位置处形成硅。使用图案化的可移除掩模限定硅位置，并且可以通过沉积或生长来施加硅，并且可以采用多晶硅或晶体硅的形式。通过在选定区域中具有厚的双层硅，显着改善了SOI器件的静电放电（ESD）特性。

95. 发明授权

US08986523B2 Biosensor capacitor 有权
标题翻译：生物传感器电容器
公开(公告)号：US08986523B2
公开(公告)日：2015-03-24
申请号：US13353523
申请日：2012-01-19
申请人： Kristin M. Ackerson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Yen Li Lim , Polina A. Razina
发明人： Kristin M. Ackerson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Yen Li Lim , Polina A. Razina
IPC分类号： G01N27/327 , G01R27/26 , G01N27/22 , H01L23/00 , H01L23/522
CPC分类号： G01N27/3276 , G01N27/22 , H01L23/5223 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/036 , H01L2224/0401 , H01L2224/04042 , H01L2224/05157 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05624 , H01L2224/13101 , H01L2224/45144 , H01L2224/45147 , H01L2224/4847 , H01L2224/48624 , H01L2224/48824 , H01L2924/12042 , H01L2924/1306 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A biosensor capacitor, including a dielectric layer; a first metal layer in the dielectric layer; a passivation layer over the dielectric layer and the first metal layer; an isolation layer over the passivation layer; a probe DNA electrode connected to the first metal layer; a counter electrode connected to the first metal layer wherein the counter electrode forms an enclosure around the probe DNA electrode; and a bond pad connected to the first metal layer.
摘要翻译：一种生物传感器电容器，包括介电层; 介电层中的第一金属层; 在所述介电层和所述第一金属层上的钝化层; 钝化层上的隔离层; 连接到第一金属层的探针DNA电极; 连接到所述第一金属层的对电极，其中所述对电极围绕所述探针DNA电极形成外壳; 以及连接到第一金属层的接合焊盘。

96. 发明授权

US08815671B2 Use of contacts to create differential stresses on devices 有权
标题翻译：使用触点在器件上产生差分应力
公开(公告)号：US08815671B2
公开(公告)日：2014-08-26
申请号：US12892474
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76834 , H01L21/76877 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/665 , H01L29/6653 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

97. 发明授权

US08716771B2 Anti-reflection structures for CMOS image sensors 有权
公开(公告)号：US08716771B2
公开(公告)日：2014-05-06
申请号：US13418706
申请日：2012-03-13
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

98. 发明申请

US20130299939A1 CHIP IDENTIFICATION PATTERN AND METHOD OF FORMING 有权
标题翻译：芯片识别模式及其形成方法
公开(公告)号：US20130299939A1
公开(公告)日：2013-11-14
申请号：US13469386
申请日：2012-05-11
申请人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
发明人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
IPC分类号： H01L27/06 , H01L21/26
CPC分类号： H01L23/544 , H01L27/08 , H01L2223/5444 , H01L2223/5446 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.
摘要翻译：公开的各种实施例包括在集成电路（IC）芯片的电平上执行双重曝光处理以形成具有嵌入的可电测量标识符的IC芯片的方法。在一些情况下，该方法包括：使用第一掩模取向曝光集成电路（IC）芯片的电平; 随后使用与第一掩模取向不同的第二掩模取向暴露IC芯片的电平; 并且开发IC芯片的电平以在IC芯片上形成可电测量的标识符。

99. 发明申请

US20130265068A1 BUILT-IN SELF-TEST METHOD AND STRUCTURE 有权
标题翻译：内置自检方法和结构
公开(公告)号：US20130265068A1
公开(公告)日：2013-10-10
申请号：US13443450
申请日：2012-04-10
申请人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
发明人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
IPC分类号： G01R31/3187
CPC分类号： G01R31/318511 , G01R31/2856 , G11C29/006 , G11C29/12 , G11C2029/1206
摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.
摘要翻译：一种半导体晶片的测试方法及相关结构。在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。

100. 发明授权

US08492214B2 Damascene metal gate and shield structure, methods of manufacture and design structures 有权
标题翻译：大马士革金属门和屏蔽结构，制造和设计结构的方法
公开(公告)号：US08492214B2
公开(公告)日：2013-07-23
申请号：US13051510
申请日：2011-03-18
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/338
CPC分类号： H01L31/0232 , G06F17/5045 , G06F17/5054 , H01L27/14632 , H01L27/14683 , H01L29/66545
摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.
摘要翻译：提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。该方法包括在虚拟栅极结构上形成介电层。该方法还包括在电介质层中形成一个或多个凹槽。该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

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