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1. 发明授权

US08460981B2 Use of contacts to create differential stresses on devices 有权
公开(公告)号：US08460981B2
公开(公告)日：2013-06-11
申请号：US12892465
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/00
CPC分类号： H01L21/76879 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/092
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

2. 发明授权

US08815671B2 Use of contacts to create differential stresses on devices 有权
标题翻译：使用触点在器件上产生差分应力
公开(公告)号：US08815671B2
公开(公告)日：2014-08-26
申请号：US12892474
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76834 , H01L21/76877 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/665 , H01L29/6653 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

3. 发明申请

US20120074502A1 USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
标题翻译：使用联系人创建设备上的差别应力
公开(公告)号：US20120074502A1
公开(公告)日：2012-03-29
申请号：US12892474
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L25/11 , H01L21/77
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76834 , H01L21/76877 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/665 , H01L29/6653 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

4. 发明授权

US08993428B2 Structure and method to create a damascene local interconnect during metal gate deposition 有权
标题翻译：在金属栅极沉积期间创建镶嵌局部互连的结构和方法
公开(公告)号：US08993428B2
公开(公告)日：2015-03-31
申请号：US12573188
申请日：2009-10-05
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/3205 , H01L21/768 , H01L29/66 , H01L29/51 , H01L27/12
CPC分类号： H01L21/76895 , H01L21/76816 , H01L27/1248 , H01L29/517 , H01L29/66545
摘要： A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.
摘要翻译：在金属栅极沉积期间创建镶嵌局部互连的方法和结构。一种方法包括：在衬底的上表面上形成栅电介质; 在栅极电介质上形成心轴; 在与心轴相同的水平上形成层间电介质（ILD）层; 在ILD层中形成沟槽; 去除心轴; 以及在栅极电介质和沟槽中形成金属层。

5. 发明申请

US20120074501A1 USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
标题翻译：使用联系人创建设备上的差别应力
公开(公告)号：US20120074501A1
公开(公告)日：2012-03-29
申请号：US12892465
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/76879 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/092
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片，与PFET的源极/漏极区域的PFET接触以及与源极/漏极区域的NFET接触的NFET。在第一实施例中，在PFET接触和PFET的源极/漏极区之间仅包含PFET接触下的硅锗（SiGe）层。在第二实施例中，PFET触点延伸到PFET的源极/漏极区域中，或者NFET触点延伸到NFET的源极/漏极区域。

6. 发明申请

US20130200910A1 3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS 有权
标题翻译：采用微机电开关的三维集成电路测试
公开(公告)号：US20130200910A1
公开(公告)日：2013-08-08
申请号：US13364345
申请日：2012-02-02
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G01R1/067 , H01L21/768
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译：一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

7. 发明授权

US08470713B2 Nitride etch for improved spacer uniformity 失效
标题翻译：氮化物蚀刻用于改善间隔物均匀性
公开(公告)号：US08470713B2
公开(公告)日：2013-06-25
申请号：US12966432
申请日：2010-12-13
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/76237 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L29/78
摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
摘要翻译：一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

8. 发明申请

US20110208482A1 Variable Focus Point Lens 有权
标题翻译：可变焦点镜头
公开(公告)号：US20110208482A1
公开(公告)日：2011-08-25
申请号：US12708561
申请日：2010-02-19
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G06F17/50 , G02B3/12
CPC分类号： G02B3/14
摘要： A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.
摘要翻译：可变焦点透镜包括透明容器，透明容器包括透明的外壳，该透明外壳包含将透明容器的内部容积分隔成上部容器部分和下部容器部分的透明柔性膜。上罐部分和下罐部分含有不同折射率的液体。透明柔性膜被静电移位以改变光路中的第一罐部分和第二罐部分的厚度，从而轴向和/或横向地移动透镜的焦点。膜的静电位移可以通过膜中的固定电荷和透明外壳上的封闭侧导电结构阵列，或透明膜上的膜侧导电结构阵列和外壳侧阵列导电结构。

9. 发明申请

US20110098838A1 SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS 有权
标题翻译：用于校正集成电路芯片的系统参数变化的系统和方法，以最小化电路有限的损失
公开(公告)号：US20110098838A1
公开(公告)日：2011-04-28
申请号：US12603679
申请日：2009-10-22
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.
摘要翻译：公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。存储处理信息和芯片的映射。处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。地图可以指示设备参数中的区域变化（例如，阈值电压）。基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

10. 发明授权

US08791712B2 3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts 有权
标题翻译：使用具有钨锥触点的MEMS开关的三维集成电路测试
公开(公告)号：US08791712B2
公开(公告)日：2014-07-29
申请号：US13364345
申请日：2012-02-02
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G01R1/067
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译：一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

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