专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20050237829A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050237829A1
公开(公告)日：2005-10-27
申请号：US11104599
申请日：2005-04-13
申请人： Hiroshi Nakamura , Tomoharu Tanaka
发明人： Hiroshi Nakamura , Tomoharu Tanaka
IPC分类号： G11C16/06 , G11C7/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/30
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/30
摘要： A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.
摘要翻译：非易失性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元单元格阵列。在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未选择的字线。将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二写入中间电压。

92. 发明申请

US20050190632A1 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line 有权
标题翻译：半导体存储器件仅使用单通道晶体管对所选字线施加电压
公开(公告)号：US20050190632A1
公开(公告)日：2005-09-01
申请号：US11115364
申请日：2005-04-27
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C11/413 , G11C16/04 , G11C16/06 , G11C16/08 , H01L27/115 , G11C8/00
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/3459 , H01L27/115
摘要： A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.
摘要翻译：本文公开的半导体存储器件包括存储单元阵列，其中存储单元以矩阵形式布置，行解码器电路用于选择该存储单元阵列中的字线并向所选字线施加电压。解码器电路包括多个第一导电类型的第一晶体管，其中每个电流路径的一端直接连接到每个字线，以及与第一导电类型相反的第二导电类型的第二晶体管，用于施加在对所选择的字线施加电压的操作时，连接到所选字线的第一晶体管的栅极的电压。对所选择的字线施加电压仅由第一导电类型的第一晶体管执行。

93. 发明申请

US20050190602A1 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US20050190602A1
公开(公告)日：2005-09-01
申请号：US11119744
申请日：2005-05-03
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/02 , G11C7/06 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

94. 发明授权

US06924690B2 Voltage switching circuit 有权
标题翻译：电压开关电路
公开(公告)号：US06924690B2
公开(公告)日：2005-08-02
申请号：US10292527
申请日：2002-11-13
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： H01L21/822 , G11C5/14 , G11C8/08 , G11C16/08 , G11C16/12 , G11C16/30 , H01L27/04 , H01L27/088 , H01L27/092 , H03K17/0814 , H03K17/10 , H03K17/693 , H03K19/003 , H03K19/0185 , H03L7/06 , H03K17/00
CPC分类号： G11C5/145 , G11C8/08 , G11C16/08 , G11C16/12 , H01L27/088 , H01L27/092 , H03K17/08142 , H03K17/102 , H03K17/693 , H03K19/00315 , H03K19/018521
摘要： A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.
摘要翻译：公开了一种电压切换电路，其由最小数量的晶体管构成，并且通过由单个耗尽型晶体管执行的高电压截止和电源电压传递函数在两个串联连接之间共享来防止阈值电压裕度降低耗尽型晶体管的栅极绝缘膜厚度或阈值电压不同。因此，在不使用涉及图案面积增加的增强型晶体管的情况下，可以提供电压切换电路，其芯片面积小，成本低，成品率和可靠性高，并且提供具有低电源电压的稳定操作，这是不可能的一个耗尽晶体管。

95. 发明申请

US20050094478A1 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050094478A1
公开(公告)日：2005-05-05
申请号：US10989372
申请日：2004-11-17
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C7/20 , G11C16/20 , G11C29/00 , G11C8/02
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

96. 发明申请

US20050094441A1 Semiconductor memory device in which source line potential is controlled in accordance with data programming mode 有权
标题翻译：根据数据编程模式控制源极线电位的半导体存储器件
公开(公告)号：US20050094441A1
公开(公告)日：2005-05-05
申请号：US11005594
申请日：2004-12-06
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G11C16/06 , G11C16/10
CPC分类号： G11C16/10 , G11C2216/16
摘要： There is provided a semiconductor memory device, which realizes rewriting of data in the memory cell by applying a potential difference between the gate and the source, or applying a potential difference between the gate and the drain, which is larger than the power supply voltage. This semiconductor memory device is provided with a source line potential control circuit configured to control the source line potential. The source line potential control circuit sets the source line potential at the time of the mode for programming “1” data in a plurality of blocks in one package to a level lower than at the normal-data programming mode.
摘要翻译：提供了一种半导体存储器件，其通过施加栅极和源极之间的电位差或施加大于电源电压的栅极和漏极之间的电位差来实现对存储器单元中的数据的重写。该半导体存储器件设置有用于控制源极线电位的源极线电位控制电路。源极线电位控制电路将用于将一个封装中的多个块中的“1”数据编程的模式的源极线电位设置为低于正常数据编程模式的电平。

97. 发明授权

US06882569B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06882569B2
公开(公告)日：2005-04-19
申请号：US10918686
申请日：2004-08-13
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G11C16/105 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C2216/14
摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.
摘要翻译：一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。

98. 发明授权

US06847524B2 Electronic apparatus having cooling unit for cooling heat-generating component 有权
标题翻译：具有用于冷却发热部件的冷却单元的电子设备
公开(公告)号：US06847524B2
公开(公告)日：2005-01-25
申请号：US10164017
申请日：2002-06-07
申请人： Kentaro Tomioka , Hiroshi Nakamura
发明人： Kentaro Tomioka , Hiroshi Nakamura
IPC分类号： G06F1/20 , H05K7/20
CPC分类号： H05K7/20154 , G06F1/203
摘要： An electronic apparatus comprises a housing containing a heat-generating component, and a cooling unit. The cooling unit includes a heat sink thermally connected to the heat-generating component, a first air passage for guiding air outside the housing to the heat sink and guiding air heated by heat exchange with the heat sink to the outside of the housing, and a second air passage for guiding air within the housing to the outside of the housing.
摘要翻译：电子设备包括容纳发热部件的壳体和冷却单元。冷却单元包括热连接到发热部件的散热器，用于将壳体外部的空气引导到散热器并将通过与散热器的热交换加热的空气引导到壳体外部的第一空气通道，以及第二空气通道，用于将壳体内的空气引导到壳体的外部。

99. 发明授权

US06836444B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US06836444B2
公开(公告)日：2004-12-28
申请号：US10452128
申请日：2003-06-03
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes a memory cell array comprising memory cell units arranged in an array form, first blocks including first memory cell units each having at least one memory cell and at least one selection gate transistor, and second blocks including second memory cell units each having at least one memory cell and at least one selection gate transistor, wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in another portion, and a structure of the first memory cell units on the end portions of the memory cell array is different from a structure of the second memory cell units.
摘要翻译：半导体存储器件包括存储单元阵列，其包括以阵列形式布置的存储单元单元，第一块包括每个具有至少一个存储单元和至少一个选择栅极晶体管的第一存储单元单元，以及包括第二存储单元单元的第二块具有至少一个存储单元和至少一个选择栅晶体管，其中所述第一块布置在所述存储单元阵列的两端部分上，所述第二块布置在另一部分中，并且所述第一存储单元单元的结构存储单元阵列的端部与第二存储单元单元的结构不同。

100. 发明授权

US06833606B2 Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor 失效
标题翻译：具有集成MIM电容器的异质结双极晶体管的制造
公开(公告)号：US06833606B2
公开(公告)日：2004-12-21
申请号：US10289684
申请日：2002-11-07
申请人： Hiroshi Nakamura , Ting Cheong Ang , Kian Siong Ang , Subrata Halder , Geok Ing Ng
发明人： Hiroshi Nakamura , Ting Cheong Ang , Kian Siong Ang , Subrata Halder , Geok Ing Ng
IPC分类号： H01L2706
CPC分类号： H01L27/0605 , H01L21/8252
摘要： In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.
摘要翻译：在本发明中，形成半导体器件，其包括位于异质结构的上表面上的MIM电容器，从其定义附近HBT的发射极，基极和集电极部分。以这种方式，电容器和HBT分别具有基本上共同的结构，HBT的基极和发射极电极分别由与上部和下部电容器板相同的金属层制成。此外，由于在定义HBT结构之前形成电容器的绝缘体区域，所以使用的电介质材料可以通过等离子体增强工艺沉积，而不会损坏HBT结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式