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1. 发明授权

US06833606B2 Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor 失效
标题翻译：具有集成MIM电容器的异质结双极晶体管的制造
公开(公告)号：US06833606B2
公开(公告)日：2004-12-21
申请号：US10289684
申请日：2002-11-07
申请人： Hiroshi Nakamura , Ting Cheong Ang , Kian Siong Ang , Subrata Halder , Geok Ing Ng
发明人： Hiroshi Nakamura , Ting Cheong Ang , Kian Siong Ang , Subrata Halder , Geok Ing Ng
IPC分类号： H01L2706
CPC分类号： H01L27/0605 , H01L21/8252
摘要： In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.
摘要翻译：在本发明中，形成半导体器件，其包括位于异质结构的上表面上的MIM电容器，从其定义附近HBT的发射极，基极和集电极部分。以这种方式，电容器和HBT分别具有基本上共同的结构，HBT的基极和发射极电极分别由与上部和下部电容器板相同的金属层制成。此外，由于在定义HBT结构之前形成电容器的绝缘体区域，所以使用的电介质材料可以通过等离子体增强工艺沉积，而不会损坏HBT结构。

2. 发明申请

US20070275538A1 Method with High Gapfill Capability for Semiconductor Devices 有权
标题翻译：半导体器件具有高插补能力的方法
公开(公告)号：US20070275538A1
公开(公告)日：2007-11-29
申请号：US11539612
申请日：2006-10-06
申请人： Ting Cheong Ang
发明人： Ting Cheong Ang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.
摘要翻译：提供了一种用于半导体器件的STI间隙填充处理的方法。在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。此外，该方法包括用第一氧化物将沟槽填充到第一深度。使用旋涂工艺填充第一氧化物。该方法还包括对沟槽内的第一氧化物进行第一致密化处理。另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

3. 发明授权

US06649517B2 Copper metal structure for the reduction of intra-metal capacitance 有权
标题翻译：铜金属结构用于降低金属间电容
公开(公告)号：US06649517B2
公开(公告)日：2003-11-18
申请号：US09859353
申请日：2001-05-18
申请人： Young-Way Teh , Victor Seng Keong Lim , Ting Cheong Ang
发明人： Young-Way Teh , Victor Seng Keong Lim , Ting Cheong Ang
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31138 , H01L21/76804 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
摘要翻译：提供了一种新的方法和结构来创建互连线。在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

4. 发明授权

US06611024B2 Method of forming PID protection diode for SOI wafer 有权
公开(公告)号：US06611024B2
公开(公告)日：2003-08-26
申请号：US09946981
申请日：2001-09-06
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203
摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

5. 发明授权

US06465296B1 Vertical source/drain contact semiconductor 有权
标题翻译：垂直源极/漏极接触半导体
公开(公告)号：US06465296B1
公开(公告)日：2002-10-15
申请号：US10167095
申请日：2002-06-10
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L218238
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66825 , H01L29/78621
摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.
摘要翻译：提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

6. 发明授权

US06406994B1 Triple-layered low dielectric constant dielectric dual damascene approach 有权
标题翻译：三层低介电常数电介质双镶嵌方法
公开(公告)号：US06406994B1
公开(公告)日：2002-06-18
申请号：US09726657
申请日：2000-11-30
申请人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
IPC分类号： H01L2144
CPC分类号： B41M5/5254 , B41M5/508 , B41M5/5218 , B41M5/5272 , Y10T428/24802
摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.
摘要翻译：描述了三层低介电常数材料双镶嵌金属化工艺。金属线被覆盖在半导体衬底上的绝缘层所覆盖。第一类型的第一介电层沉积在绝缘层上。第二类型的第二介电层沉积在第一介电层上。通孔图案被蚀刻到第二介电层中。此后，第一类型的第三电介质层沉积在图案化的第二介电层上。同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

7. 发明授权

US08110502B2 Method of improving adhesion strength of low dielectric constant layers 有权
标题翻译：提高低介电常数层粘附强度的方法
公开(公告)号：US08110502B2
公开(公告)日：2012-02-07
申请号：US11394529
申请日：2006-03-30
申请人： Ting Cheong Ang
发明人： Ting Cheong Ang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76825 , H01L21/76831 , H01L21/7685 , H01L21/76862
摘要： A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.
摘要翻译：提供一种制造半导体器件的方法。在具体实施例中，该方法包括提供具有表面区域的半导体衬底。表面区域包括覆盖半导体衬底的一个或多个层。此外，该方法包括形成覆盖表面区域并形成覆盖在电介质层上的扩散阻挡层的电介质层。此外，该方法包括使扩散阻挡层经受等离子体环境以促进在界面区域处的扩散阻挡层和电介质层之间的粘附。此外，该方法包括处理半导体衬底，同时保持介电层和界面区域处的扩散阻挡层之间的附着。将扩散阻挡层经受等离子体环境包括保持阻挡扩散层的厚度。

8. 发明授权

US08026151B2 Method with high gapfill capability for semiconductor devices 有权
标题翻译：半导体器件具有高填隙能力的方法
公开(公告)号：US08026151B2
公开(公告)日：2011-09-27
申请号：US12273323
申请日：2008-11-18
申请人： Ting Cheong Ang
发明人： Ting Cheong Ang
IPC分类号： H01L21/00
CPC分类号： H01L21/76224
摘要： A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.
摘要翻译：提供了一种用于半导体器件的STI间隙填充处理的方法。在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。此外，该方法包括用第一氧化物将沟槽填充到第一深度。使用旋涂工艺填充第一氧化物。该方法还包括对沟槽内的第一氧化物进行第一致密化处理。另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

9. 发明授权

US07910475B2 Method for forming low dielectric constant fluorine-doped layers 有权
标题翻译：低介电常数氟掺杂层的形成方法
公开(公告)号：US07910475B2
公开(公告)日：2011-03-22
申请号：US12505414
申请日：2009-07-17
申请人： Ting Cheong Ang
发明人： Ting Cheong Ang
IPC分类号： H01L21/00
CPC分类号： H01L21/02131 , C23C16/30 , H01L21/02274 , H01L21/02362 , H01L21/31604 , H01L21/31629 , H01L21/31633 , H01L21/7684 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.
摘要翻译：提供一种形成半导体器件的方法。在一个实施例中，该方法包括提供具有表面区域的半导体衬底。表面区域包括覆盖半导体衬底的一个或多个层。此外，该方法包括沉积覆盖表面区域的介电层。介电层通过CVD工艺形成。此外，该方法包括形成覆盖在电介质层上的扩散阻挡层。此外，该方法包括形成覆盖扩散阻挡层的导电层。另外，该方法包括使用化学机械抛光工艺来减小导电层的厚度。 CVD工艺利用氟作为反应物形成电介质层。此外，介电层与等于或小于3.3的介电常数相关联。

10. 发明申请

US20100006975A1 METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH 有权
标题翻译：在间隔层中消除微孔的方法
公开(公告)号：US20100006975A1
公开(公告)日：2010-01-14
申请号：US12258366
申请日：2008-10-24
申请人： Ting Cheong Ang
发明人： Ting Cheong Ang
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供具有衬底区域的半导体衬底。该方法还包括形成覆盖衬底区域的衬垫氧化物层。该方法还包括形成覆盖衬垫氧化物层的阻挡层。此外，该方法包括图案化停止层和衬垫氧化物层以暴露衬底区域的一部分。此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁，底部和高度。此外，该方法包括沉积氧化物和氮化硅的交替层以至少填充沟槽，氧化物通过HDP-CVD工艺沉积。该方法另外包括执行平坦化处理以去除一部分氮化硅和氧化物层。此外，该方法包括去除衬垫氧化物并停止层。

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