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1. 发明授权

US07619921B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07619921B2
公开(公告)日：2009-11-17
申请号：US11530551
申请日：2006-09-11
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/06
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

2. 发明申请

US20070016738A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20070016738A1
公开(公告)日：2007-01-18
申请号：US11530551
申请日：2006-09-11
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00 , G06F9/00 , G06F15/177 , G11C16/06 , G11C11/34
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

3. 发明授权

US07126851B2 Method of transferring initially-setting data in a non-volatile semiconductor memory 有权
标题翻译：在非易失性半导体存储器中传送初始设置数据的方法
公开(公告)号：US07126851B2
公开(公告)日：2006-10-24
申请号：US10989372
申请日：2004-11-17
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/06
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

4. 发明授权

US06831859B2 Non-volatile semiconductor memory for storing initially-setting data 有权
标题翻译：用于存储初始设置数据的非易失性半导体存储器
公开(公告)号：US06831859B2
公开(公告)日：2004-12-14
申请号：US10703503
申请日：2003-11-10
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C1606
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

5. 发明授权

US06462985B2 Non-volatile semiconductor memory for storing initially-setting data 有权
标题翻译：用于存储初始设置数据的非易失性半导体存储器
公开(公告)号：US06462985B2
公开(公告)日：2002-10-08
申请号：US09731910
申请日：2000-12-08
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C1606
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

6. 发明申请

US20050094478A1 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050094478A1
公开(公告)日：2005-05-05
申请号：US10989372
申请日：2004-11-17
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C7/20 , G11C16/20 , G11C29/00 , G11C8/02
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

7. 发明授权

US06704223B2 Non-volatile semiconductor memory 有权
公开(公告)号：US06704223B2
公开(公告)日：2004-03-09
申请号：US10241468
申请日：2002-09-12
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C1606
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

8. 发明授权

US6097638A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6097638A
公开(公告)日：2000-08-01
申请号：US22014
申请日：1998-02-11
申请人： Toshihiko Himeno , Kazushige Kanda , Hiroshi Nakamura
发明人： Toshihiko Himeno , Kazushige Kanda , Hiroshi Nakamura
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C16/26
摘要： An EEPROM employs, as a scheme of detecting data of a memory cell in a memory cell array, a scheme of detecting the potential of a bit line potential sense node, which depends on the relationship in amplitude between the current for charging a bit line from a current source and the discharge current flowing to a selected cell using a sense amplifier. The sense amplifier is arranged in correspondence with one bit line and includes a constant current source transistor for charging the corresponding bit line, a latch circuit for latching memory cell data read out to the bit line potential sense node, and a switch transistor for turning on/off the charge path to the bit line based on data of the latch circuit. In the verify read mode, the cell current between the Vcc node and Vss node of a cell not to be written or a completely written cell can be turned off, so verification can be performed without flowing any unnecessary current.
摘要翻译：作为检测存储单元阵列中的存储单元的数据的方案，EEPROM采用检测位线电位检测节点的电位的方案，该方案取决于用于对位线的充电电流之间的幅度的关系，电流源和使用读出放大器流向选定单元的放电电流。读出放大器与一个位线相对应地布置，并且包括用于对相应位线充电的恒流源晶体管，用于锁存读出到位线电位检测节点的存储单元数据的锁存电路和用于导通的开关晶体管 /根据锁存电路的数据关闭位线的充电路径。在验证读取模式下，可以关闭不要写入的单元的Vcc节点和Vss节点之间的单元电流，或者完全写入单元的单元电流可以被关闭，因此可以在不流过任何不必要的电流的情况下执行验证。

9. 发明授权

US06240022B1 Non-volatile semiconductor memory device with block erase function 失效
标题翻译：具有块擦除功能的非易失性半导体存储器件
公开(公告)号：US06240022B1
公开(公告)日：2001-05-29
申请号：US09055215
申请日：1998-04-06
申请人： Koji Sakui , Hiroshi Nakamura , Toshihiko Himeno , Junichi Miyamoto
发明人： Koji Sakui , Hiroshi Nakamura , Toshihiko Himeno , Junichi Miyamoto
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： At the time of erasing data, common gate lines connected to selective gates are charged with Vcc or a voltage higher than. This enables reliable cut-off of transfer transistors at the time of erasing data. Accordingly, even if the potential of the selective gates increase in accordance with an increase in the substrate potential of a memory cell portion, current leakage through the transistors can be prevented. Further, at the time of erasing data, the common gate lines are set to VL slightly higher than Vss. This can enhance the cut-off characteristics of transfer transistors in a non-selected block, and prevent erroneous erasion of data stored in memory cells included in the non-selected block.
摘要翻译：在擦除数据时，连接到选择栅极的公共栅极线用Vcc或高于电压的电压充电。这样可以在擦除数据时切换传输晶体管。因此，即使选择栅极的电位根据存储单元部分的衬底电位的增加而增加，也可以防止通过晶体管的漏电流。此外，在擦除数据时，将公共栅极线设置为略高于Vss的VL。这可以增强非选择块中的转移晶体管的截止特性，并且防止存储在未选择块中的存储单元中的数据的错误擦除。

10. 发明授权

US5818756A Non-volatile semiconductor memory device with block erase function 失效
标题翻译：具有块擦除功能的非易失性半导体存储器件
公开(公告)号：US5818756A
公开(公告)日：1998-10-06
申请号：US631049
申请日：1996-04-12
申请人： Koji Sakui , Hiroshi Nakamura , Toshihiko Himeno , Junichi Miyamoto
发明人： Koji Sakui , Hiroshi Nakamura , Toshihiko Himeno , Junichi Miyamoto
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/16 , G11C16/00
CPC分类号： G11C16/16
摘要： At the time of erasing data, common gate lines connected to selective gates are charged with Vcc or a voltage higher than. This enables reliable cut-off of transfer transistors at the time of erasing data. Accordingly, even if the potential of the selective gates increase in accordance with an increase in the substrate potential of a memory cell portion, current leakage through the transistors can be prevented. Further, at the time of erasing data, the common gate lines are set to V.sub.L slightly higher than Vss. This can enhance the cut-off characteristics of transfer transistors in a non-selected block, and prevent erroneous erasion of data stored in memory cells included in the non-selected block.
摘要翻译：在擦除数据时，连接到选择栅极的公共栅极线用Vcc或高于电压的电压充电。这样可以在擦除数据时切换传输晶体管。因此，即使选择栅极的电位根据存储单元部分的衬底电位的增加而增加，也可以防止通过晶体管的漏电流。此外，在擦除数据时，将公共栅极线设置为略高于Vss的VL。这可以增强非选择块中的转移晶体管的截止特性，并且防止存储在未选择块中的存储单元中的数据的错误擦除。

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