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    • 2. 发明授权
    • Non-volatile semiconductor memory
    • 非易失性半导体存储器
    • US08144513B2
    • 2012-03-27
    • US12960882
    • 2010-12-06
    • Koji HosonoHiroshi NakamuraKen TakeuchiKenichi Imamiya
    • Koji HosonoHiroshi NakamuraKen TakeuchiKenichi Imamiya
    • G11C11/34G11C16/06
    • G11C16/0483G11C5/145G11C7/1006G11C11/5621G11C11/5628G11C11/5635G11C11/5642G11C16/10G11C16/24G11C16/26G11C16/3445G11C16/3454G11C16/3459G11C2211/5621G11C2211/5641G11C2211/5642G11C2211/5643
    • A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
    • 非易失性半导体器件具有存储单元阵列,其具有电可擦除可编程非易失性存储器单元,重新编程和检索电路,其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中,使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索,以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中,根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。
    • 3. 发明申请
    • Non-Volatile Semiconductor Memory
    • 非易失性半导体存储器
    • US20110075488A1
    • 2011-03-31
    • US12960882
    • 2010-12-06
    • Koji HosonoHiroshi NakamuraKen TakeuchiKenichi Imamiya
    • Koji HosonoHiroshi NakamuraKen TakeuchiKenichi Imamiya
    • G11C16/04
    • G11C16/0483G11C5/145G11C7/1006G11C11/5621G11C11/5628G11C11/5635G11C11/5642G11C16/10G11C16/24G11C16/26G11C16/3445G11C16/3454G11C16/3459G11C2211/5621G11C2211/5641G11C2211/5642G11C2211/5643
    • A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
    • 非易失性半导体器件具有存储单元阵列,其具有电可擦除可编程非易失性存储器单元,重新编程和检索电路,其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中,使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索,以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中,根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。