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91. 发明申请

US20080215790A1 Memory systems for automated computing machinery 失效
标题翻译：自动计算机的存储系统
公开(公告)号：US20080215790A1
公开(公告)日：2008-09-04
申请号：US12102034
申请日：2008-04-14
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F13/36
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：提供体现在机器可读介质中的设计结构。设计结构的实施例包括存储器系统，包括：存储器控制器; 一个内存总线终端; 将存储器控制器，存储器总线终端器和至少一个存储器模块互连的高速存储器总线; 和所述至少一个存储器模块，所述存储器模块包括至少一个存储器集线器设备，由所述存储器集线器设备服务的高速随机存取存储器，两个总线信号端口以及在所述存储器模块上制造的所述高速存储器总线的段以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器设备。

92. 发明申请

US20080212282A1 METHOD AND APPARATUS FOR COOLING AN EQUIPMENT ENCLOSURE THROUGH CLOSED-LOOP LIQUID-ASSISTED AIR COOLING IN COMBINATION WITH DIRECT LIQUID COOLING 审中-公开
公开(公告)号：US20080212282A1
公开(公告)日：2008-09-04
申请号：US12042596
申请日：2008-03-05
申请人： Shawn A. Hall , Shurong Tian , Paul W. Coteus , John P. Karidis , Evan G. Colgan , Robert W. Guernsey
发明人： Shawn A. Hall , Shurong Tian , Paul W. Coteus , John P. Karidis , Evan G. Colgan , Robert W. Guernsey
IPC分类号： H05K7/20
CPC分类号： H05K7/20754 , G06F1/20 , G06F2200/201
摘要： A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.

93. 发明申请

US20080176419A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 失效
公开(公告)号：US20080176419A1
公开(公告)日：2008-07-24
申请号：US11865436
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

94. 发明申请

US20080163487A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
公开(公告)号：US20080163487A1
公开(公告)日：2008-07-10
申请号：US12047622
申请日：2008-03-13
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H05K3/00 , H01R9/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

95. 发明申请

US20080155821A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
标题翻译：土地网阵列（LGA）利用金属激光器热电偶和其他多点接触几何
公开(公告)号：US20080155821A1
公开(公告)日：2008-07-03
申请号：US12047552
申请日：2008-03-13
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H05K3/36
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机

96. 发明授权

US07342789B2 Method and apparatus for cooling an equipment enclosure through closed-loop, liquid-assisted air cooling in combination with direct liquid cooling 有权
标题翻译：通过闭环，液体辅助空气冷却与直接液体冷却结合来冷却设备外壳的方法和设备
公开(公告)号：US07342789B2
公开(公告)日：2008-03-11
申请号：US11427384
申请日：2006-06-29
申请人： Shawn A. Hall , Shurong Tian , Paul W. Coteus , John P. Karidis , Evan G. Colgan , Robert W. Guernsey, Jr.
发明人： Shawn A. Hall , Shurong Tian , Paul W. Coteus , John P. Karidis , Evan G. Colgan , Robert W. Guernsey, Jr.
IPC分类号： H05K7/20 , F28D15/00 , F28F7/00
CPC分类号： H05K7/20754 , G06F1/20 , G06F2200/201
摘要： A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.
摘要翻译：优选地在外壳内冷却发热部件的多样性的方法和装置，其中至少一些部件具有高功率密度，而其它部件具有低功率密度。由基本相对较少的高功率密度组件（例如微处理器芯片）产生的热量通过直接液体冷却而被去除，而由更多的低功率或低功率密度组件产生的热量，例如存储芯片例如，通过液体辅助空气冷却以封闭回路的形式除去，包括沿着空气路径交替的多个加热和冷却区域。

97. 发明申请

US20070276977A1 SYSTEMS AND METHODS FOR PROVIDING MEMORY MODULES WITH MULTIPLE HUB DEVICES 有权
标题翻译：用多个集线器件提供存储器模块的系统和方法
公开(公告)号：US20070276977A1
公开(公告)日：2007-11-29
申请号：US11420046
申请日：2006-05-24
申请人： Paul W. Coteus , Warren E. Maule , Edward J. Seminaro , Robert B. Tremaine
发明人： Paul W. Coteus , Warren E. Maule , Edward J. Seminaro , Robert B. Tremaine
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.
摘要翻译：为多个集线器设备提供内存模块的系统和方法。示例性系统包括具有存储器总线的级联互连存储器系统，存储器控制器和存储器模块。存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。存储器模块包括具有三个或更多个端口的第一集线器设备和具有三个或更多个端口的第二集线器设备。第一集线器设备上的第一端口经由存储器总线与存储器控制器通信，第一集线器设备上的第二端口与第一组存储器设备通信，第一集线器设备上的第三端口级联连接到第二集线器设备上的第一端口。第二集线器设备上的第二端口与第二组存储器设备通信，并且第二集线器设备上的第三端口支持与存储器系统中的后续集线器设备的级联连接。

98. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

99. 发明授权

US09077616B2 T-star interconnection network topology 有权
标题翻译： T星互连网络拓扑
公开(公告)号：US09077616B2
公开(公告)日：2015-07-07
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/24 , H04L12/715
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

100. 发明申请

US20140071778A1 MEMORY DEVICE REFRESH 有权
标题翻译：存储设备刷新
公开(公告)号：US20140071778A1
公开(公告)日：2014-03-13
申请号：US13609655
申请日：2012-09-11
申请人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
发明人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
IPC分类号： G11C11/402
CPC分类号： G11C11/40611 , G06F13/1668 , Y02D10/14
摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.
摘要翻译：根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。基于接收到同步命令，内存刷新定时器在存储器设备内复位。基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

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