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91. 发明申请

US20120119257A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20120119257A1
公开(公告)日：2012-05-17
申请号：US13361051
申请日：2012-01-30
申请人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L29/73
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

92. 发明申请

US20120091530A1 Low trigger voltage electrostatic discharge NFET in triple well CMOS technology 有权
标题翻译：低触发电压静电放电NFET三阱CMOS技术
公开(公告)号：US20120091530A1
公开(公告)日：2012-04-19
申请号：US12907105
申请日：2010-10-19
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0274
摘要： An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.
摘要翻译：用于集成电路的静电放电（ESD）保护装置包括形成在第二极性类型的衬底中的第一极性类型的掩埋层。第二极性类型的阱区形成在掩埋层的上方。在阱区内形成第一极性类型的FET。第一极性类型的内部一对浅阱设置在FET的源极和漏极扩散区附近，内部一对浅阱具有使得内部一对浅井的底部高于埋层第一极性类型的一对深阱对向下延伸到掩埋层的顶部，使得外部一对深阱和掩埋层限定第二极性类型的阱区的周边。

93. 发明申请

US20120049321A1 PROGRAMMABLE ELECTRICAL FUSE 失效
标题翻译：可编程电气保险丝
公开(公告)号：US20120049321A1
公开(公告)日：2012-03-01
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/525 , H01L21/326
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

94. 发明授权

US07826188B2 Methods, design structures, and systems for current mode logic (CML) differential driver ESD protection circuitry 失效
标题翻译：电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统
公开(公告)号：US07826188B2
公开(公告)日：2010-11-02
申请号：US12140485
申请日：2008-06-17
申请人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译：在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

95. 发明申请

US20100246076A1 Electrical Overstress Protection Circuit 有权
标题翻译：电气过载保护电路
公开(公告)号：US20100246076A1
公开(公告)日：2010-09-30
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译：提供了一种用于电力过应力（EOS）保护的半导体电路。半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

96. 发明申请

US20090268359A1 ELECTROSTATIC DISCHARGE POWER CLAMP WITH IMPROVED ELECTRICAL OVERSTRESS ROBUSTNESS 审中-公开
标题翻译：静电放电电源钳具有改进的电气过载稳定性
公开(公告)号：US20090268359A1
公开(公告)日：2009-10-29
申请号：US12109820
申请日：2008-04-25
申请人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li
发明人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) and electrical overstress (EOS) events includes a resistor/capacitor (RC) triggering device configured between a pair of power rails; a silicon controlled rectifier (SCR) triggered by the RC triggering device during an ESD event, wherein the SCR, when activated, acts as a power rail voltage clamp; and a field effect transistor (FET) coupled between the RC triggering device and the SCR, wherein the FET serves as an integrated part of the RC triggering device that triggers the SCR during the ESD event; and wherein the FET also operates in a snapback mode to trigger the SCR during an EOS event that is slower in comparison to the ESD event such that the EOS event would not otherwise cause triggering of the SCR via the RC triggering device itself.
摘要翻译：用于保护集成电路免受静电放电（ESD）和电过载（EOS）事件的装置包括：在一对电源轨之间配置的电阻/电容器（RC）触发装置; 在ESD事件期间由RC触发装置触发的可控硅整流器（SCR），其中所述SCR在被激活时用作电力轨道电压钳位; 以及耦合在RC触发装置和SCR之间的场效应晶体管（FET），其中所述FET用作在ESD事件期间触发SCR的RC触发装置的集成部分; 并且其中所述FET还以快速恢复模式操作以在与ESD事件相比较慢的EOS事件期间触发SCR，使得EOS事件不会通过RC触发装置本身引起触发SCR。

97. 发明申请

US20090225481A1 E-Fuse Used to Disable a Triggering Network 失效
标题翻译：电子保险丝用于禁用触发网络
公开(公告)号：US20090225481A1
公开(公告)日：2009-09-10
申请号：US12041962
申请日：2008-03-04
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A device and/or circuit having an e-fuse is provided to disable a triggering network, and more specifically, an e-fuse is used to disable an electrostatic discharge (ESD) RC triggering network after device installation. The device and/or circuit includes a triggering network electrically coupled to an electrostatic discharge (ESD) protection device. An e-fuse is electrically coupled with the triggering network and configured to render the ESD protection device insensitive to a triggering signal after blowing the e-fuse.
摘要翻译：提供具有电子保险丝的装置和/或电路以禁用触发网络，更具体地，使用电子熔丝来在设备安装之后禁用静电放电（ESD）RC触发网络。该装置和/或电路包括电耦合到静电放电（ESD）保护装置的触发网络。电子熔丝与触发网络电耦合并且被配置为使得ESD保护装置在吹动电熔丝之后对触发信号不敏感。

98. 发明申请

US20090179268A1 DESIGN STRUCTURES FOR HIGH-VOLTAGE INTEGRATED CIRCUITS 失效
标题翻译：高压集成电路的设计结构
公开(公告)号：US20090179268A1
公开(公告)日：2009-07-16
申请号：US12059034
申请日：2008-03-31
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
IPC分类号： H01L29/786 , G06F17/50
CPC分类号： H01L27/1203
摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.
摘要翻译：高压集成电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将第一和第二栅极电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

99. 发明授权

US07399665B2 Electrostatic discharge protection device and method of fabricating same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US07399665B2
公开(公告)日：2008-07-15
申请号：US11781370
申请日：2007-07-23
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

100. 发明申请

US20120004896A1 COMPONENT BEHAVIOR MODELING USING SEPARATE BEHAVIOR MODEL 有权
标题翻译：使用分离行为模型的组件行为建模
公开(公告)号：US20120004896A1
公开(公告)日：2012-01-05
申请号：US12826958
申请日：2010-06-30
申请人： Junjun Li , Rahul Nayak
发明人： Junjun Li , Rahul Nayak
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5045 , G06F17/5068
摘要： A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.
摘要翻译：提供了行为模型，其被配置为模拟除了组件的组件模型之外的组件的行为的一个方面。行为模型可以包含在用于模拟电路运行的电路模型中。电路模型可以包括组件的组件模型和与组件模型并联或串联的对应行为模型。组件模型和行为模型可以共同模拟电路中组件的所有行为。在一个实施例中，行为模型模拟组件所呈现的回弹行为。

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