专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130009207A1 VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS 有权
标题翻译：三维CMOS工艺中的垂直NPNP结构
公开(公告)号：US20130009207A1
公开(公告)日：2013-01-10
申请号：US13614072
申请日：2012-09-13
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/74
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

2. 发明申请

US20130020645A1 ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR 有权
标题翻译： ESD场效应晶体管和集成扩散电阻
公开(公告)号：US20130020645A1
公开(公告)日：2013-01-24
申请号：US13188094
申请日：2011-07-21
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Rahul Mishra , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Rahul Mishra , Junjun Li , Mujahid Muhammad
IPC分类号： H01L29/772 , G06F9/45 , H01L21/336
CPC分类号： H01L29/41775 , H01L27/0266 , H01L29/1087 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
摘要翻译：静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

3. 发明申请

US20120305984A1 SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS 失效
标题翻译：用于ESD保护集成电路的SCR / MOS钳位
公开(公告)号：US20120305984A1
公开(公告)日：2012-12-06
申请号：US13149174
申请日：2011-05-31
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/747 , G06F17/50 , H01L21/332
CPC分类号： H01L29/742 , H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.
摘要翻译：静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。可以在p阱中形成NFET，并且可以在n阱中形成PFET。在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

4. 发明申请

US20130057991A1 SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL 有权
标题翻译：硅控制整流器结构具有改进的断路和漏电控制
公开(公告)号：US20130057991A1
公开(公告)日：2013-03-07
申请号：US13226838
申请日：2011-09-07
申请人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Alain Loiseau
发明人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Alain Loiseau
IPC分类号： H02H9/04 , H01L21/332 , G06F17/50 , H01L29/74
CPC分类号： H01L29/66363 , G06F17/50 , H01L27/0262 , H01L29/74 , H01L29/7436 , H02H9/04
摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.
摘要翻译：可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。第一层横向定位在与第一p-n结垂直对准的顶表面上。第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。包括第二层的材料具有比包含第一层的材料更高的电阻率。

5. 发明申请

US20120126285A1 Vertical NPNP Structure In a Triple Well CMOS Process 有权
标题翻译：三井CMOS工艺中的垂直NPNP结构
公开(公告)号：US20120126285A1
公开(公告)日：2012-05-24
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/74 , G06F17/50 , H01L21/332
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

6. 发明申请

US20120250195A1 ELECTROSTATIC DISCHARGE POWER CLAMP WITH A JFET BASED RC TRIGGER CIRCUIT 有权
标题翻译：静电放电电源钳位与基于JFET的RC触发电路
公开(公告)号：US20120250195A1
公开(公告)日：2012-10-04
申请号：US13076625
申请日：2011-03-31
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.
摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET）电阻器作为RC网络的电阻元件。

7. 发明申请

US20120178222A1 SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
标题翻译：硅控制整流器（SCR），制造方法和设计结构
公开(公告)号：US20120178222A1
公开(公告)日：2012-07-12
申请号：US12985840
申请日：2011-01-06
申请人： Michel J. ABOU-KHALIL , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li
发明人： Michel J. ABOU-KHALIL , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H01L21/33 , G06F17/50
CPC分类号： H01L27/0262 , G06F17/5045 , H01L29/0649 , H01L29/0839 , H01L29/66393 , H01L29/7436
摘要： Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.
摘要翻译：本文公开了可控硅整流器（SCR），制造方法和设计结构。该方法包括在绝缘体上硅（SOI）晶片的掩埋绝缘体层上形成公共P阱。该方法还包括在P阱中形成多个可控硅整流器（SCR），使得多个SCR中的每一个的N +扩散阴极通过公共P阱耦合在一起。

8. 发明申请

US20120091530A1 Low trigger voltage electrostatic discharge NFET in triple well CMOS technology 有权
标题翻译：低触发电压静电放电NFET三阱CMOS技术
公开(公告)号：US20120091530A1
公开(公告)日：2012-04-19
申请号：US12907105
申请日：2010-10-19
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0274
摘要： An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.
摘要翻译：用于集成电路的静电放电（ESD）保护装置包括形成在第二极性类型的衬底中的第一极性类型的掩埋层。第二极性类型的阱区形成在掩埋层的上方。在阱区内形成第一极性类型的FET。第一极性类型的内部一对浅阱设置在FET的源极和漏极扩散区附近，内部一对浅阱具有使得内部一对浅井的底部高于埋层第一极性类型的一对深阱对向下延伸到掩埋层的顶部，使得外部一对深阱和掩埋层限定第二极性类型的阱区的周边。

9. 发明申请

US20100246076A1 Electrical Overstress Protection Circuit 有权
标题翻译：电气过载保护电路
公开(公告)号：US20100246076A1
公开(公告)日：2010-09-30
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译：提供了一种用于电力过应力（EOS）保护的半导体电路。半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

10. 发明申请

US20090268359A1 ELECTROSTATIC DISCHARGE POWER CLAMP WITH IMPROVED ELECTRICAL OVERSTRESS ROBUSTNESS 审中-公开
标题翻译：静电放电电源钳具有改进的电气过载稳定性
公开(公告)号：US20090268359A1
公开(公告)日：2009-10-29
申请号：US12109820
申请日：2008-04-25
申请人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li
发明人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) and electrical overstress (EOS) events includes a resistor/capacitor (RC) triggering device configured between a pair of power rails; a silicon controlled rectifier (SCR) triggered by the RC triggering device during an ESD event, wherein the SCR, when activated, acts as a power rail voltage clamp; and a field effect transistor (FET) coupled between the RC triggering device and the SCR, wherein the FET serves as an integrated part of the RC triggering device that triggers the SCR during the ESD event; and wherein the FET also operates in a snapback mode to trigger the SCR during an EOS event that is slower in comparison to the ESD event such that the EOS event would not otherwise cause triggering of the SCR via the RC triggering device itself.
摘要翻译：用于保护集成电路免受静电放电（ESD）和电过载（EOS）事件的装置包括：在一对电源轨之间配置的电阻/电容器（RC）触发装置; 在ESD事件期间由RC触发装置触发的可控硅整流器（SCR），其中所述SCR在被激活时用作电力轨道电压钳位; 以及耦合在RC触发装置和SCR之间的场效应晶体管（FET），其中所述FET用作在ESD事件期间触发SCR的RC触发装置的集成部分; 并且其中所述FET还以快速恢复模式操作以在与ESD事件相比较慢的EOS事件期间触发SCR，使得EOS事件不会通过RC触发装置本身引起触发SCR。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式