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91. 发明授权

US06535965B1 Semiconductor memory device with fast masking process in burst write mode 有权
标题翻译：具有突发写入模式的快速掩蔽处理的半导体存储器件
公开(公告)号：US06535965B1
公开(公告)日：2003-03-18
申请号：US09559099
申请日：2000-04-27
申请人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
发明人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1006 , G11C2207/229
摘要： A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
摘要翻译：半导体存储器件具有突发写入模式，其中通过多个命令焊盘输入预定的多个命令信号，并且响应于命令信号执行脉冲串写入模式中的掩码控制操作。因此，突发写入模式中的掩码控制的速度提高，从而提高数据传输速率。

92. 发明授权

US06525570B2 Input/output interfacing circuit, input/output interface, and semiconductor device having input/output interfacing circuit 有权
公开(公告)号：US06525570B2
公开(公告)日：2003-02-25
申请号：US09820719
申请日：2001-03-30
申请人： Yoshimasa Yagishita , Toshiya Uchida
发明人： Yoshimasa Yagishita , Toshiya Uchida
IPC分类号： H03K190175
CPC分类号： H03K19/0002 , H03K19/017509
摘要： The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

93. 发明授权

US06353561B1 Semiconductor integrated circuit and method for controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06353561B1
公开(公告)日：2002-03-05
申请号：US09397845
申请日：1999-09-17
申请人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
发明人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.
摘要翻译：诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。这允许在外部时钟的每个周期获取多于一个外部命令。获取的外部命令被提供给命令解码器进行解码。当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

94. 发明授权

US06330682B1 Semiconductor memory device achieving faster operation based on earlier timings of latch operations 失效
标题翻译：半导体存储器件基于较早的锁存操作定时实现更快的操作
公开(公告)号：US06330682B1
公开(公告)日：2001-12-11
申请号：US09104374
申请日：1998-06-25
申请人： Kazuyuki Kanazashi , Naoharu Shinozaki , Toshiya Uchida
发明人： Kazuyuki Kanazashi , Naoharu Shinozaki , Toshiya Uchida
IPC分类号： G06F104
CPC分类号： G11C8/18
摘要： A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.
摘要翻译：具有内部电路的半导体存储器件包括命令解码器，其对输入命令信号进行解码以提供解码命令信号，地址锁存信号产生电路比命令解码器运行得更快，将输入命令信号解码为提供地址锁存信号，以及基于解码指令信号控制内部电路的控制电路。半导体存储器件还包括地址输入电路，其响应于地址锁存信号而锁存地址信号。

95. 发明授权

US06270400B1 Door mechanism for automobile air conditioner 有权
标题翻译：汽车空调门机构
公开(公告)号：US06270400B1
公开(公告)日：2001-08-07
申请号：US09284025
申请日：1999-04-06
申请人： Akihiro Tsurushima , Takumi Ijichi , Katsuhiro Kurokawa , Toshiya Uchida , Masaharu Onda
发明人： Akihiro Tsurushima , Takumi Ijichi , Katsuhiro Kurokawa , Toshiya Uchida , Masaharu Onda
IPC分类号： B60S154
CPC分类号： B60H1/00857 , B60H1/00692
摘要： A mix door D, which is arranged in a limited space defined between an upstream air passage 10 in which an evaporator 3 is installed and a downstream air passage 11 in which a heater core 4 is installed, is of a sliding type. By guiding a door proper 12 by using a cam groove, a seal member 15 bonded to the door proper 12 is pressed against a contacting member 13 only when the door proper 12 assumes its close position. Smoothed operation of the door proper 12 is achieved with a compact construction of a unit, and sealing and temperature controlling performance is increased.
摘要翻译：设置在设置有蒸发器3的上游空气通道10和安装有加热器芯4的下游空气通道11之间的有限空间中的混合门D是滑动型的。通过使用凸轮槽引导门本体12，仅当门本体12处于其关闭位置时，结合到门本体12的密封构件15被压靠在接触构件13上。门体12的平滑操作通过单元的紧凑结构实现，并且密封和温度控制性能增加。

96. 发明授权

US06048263A Heating, ventilation, and air conditioning unit for automotive vehicles 失效
标题翻译：汽车加热，通风和空调机组
公开(公告)号：US06048263A
公开(公告)日：2000-04-11
申请号：US106206
申请日：1998-06-29
申请人： Toshiya Uchida , Toshiyuki Yoshida , Katsuaki Koshida , Katsuhiro Kurokawa
发明人： Toshiya Uchida , Toshiyuki Yoshida , Katsuaki Koshida , Katsuhiro Kurokawa
IPC分类号： B60H1/00 , B60H1/32
CPC分类号： B60H1/00678 , B60H1/00064 , B60H1/00692 , B60H1/00842 , B60H2001/00164 , B60H2001/002
摘要： An automobile heating, ventilation, and air conditioning (HVAC) unit comprises a heating, ventilation, and air conditioning case permitting the flow of interior air, an evaporator core disposed in the case for taking heat from the interior air to produce cool air, a heater core disposed in the case downstream of the evaporator core for adding heat to the cool air to produce warm air, an air mix chamber defined in the case for blending the cool air with the warm air, an air mix door disposed between the evaporator core and the heater core for controlling the percentage of the cool air and the warm air being fed into the air mix chamber, depending on the position of the air mix door, and a foot-vent communication passage defined in the case by partitioning the rear end of the air mix chamber by a partition wall extending substantially vertically along the inner wall of the case, so that the foot-vent communication passage communicates with the downstream end of the air mix chamber. The case has foot vent outlets at the lower end of the foot-vent communication passage.
摘要翻译：汽车加热，通风和空调（HVAC）单元包括允许内部空气流动的加热，通风和空调箱，设置在壳体中用于从内部空气吸收热量以产生冷空气的蒸发器芯，加热器芯设置在蒸发器核心的下游，用于向冷空气加热以产生温暖的空气;空气混合室，限定在用于将冷空气与暖空气混合的壳体中;空气混合门，设置在蒸发器核心以及加热器芯，用于根据空气混合门的位置控制冷空气和暖空气进入空气混合室的百分比，以及通过将后端分隔开的底部通气连通通道通过沿着壳体的内壁基本上垂直延伸的分隔壁，使得空气混合室与空气混合室的下游端连通。该壳体在脚部通气连通通道的下端具有排气口。

97. 发明授权

US5926046A Semiconductor integrated circuit employing smaller number of elements to provide phase-locked clock signal 失效
标题翻译：半导体集成电路采用较少数量的元件来提供锁相时钟信号
公开(公告)号：US5926046A
公开(公告)日：1999-07-20
申请号：US794499
申请日：1997-02-04
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G11C11/407 , G06F1/10 , G06F15/78 , G11C7/22 , H03L7/00 , H03L7/081 , H03K5/04
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , H03L7/0814
摘要： A semiconductor integrated circuit has a voltage generator, a delay gate array, and a current controller. The voltage generator generates an output voltage in response to voltage control signals. The delay gate array has cascaded delay gates for producing a delay. The current controller controls a current flowing to the delay gate array in response to the output voltage of the voltage generator. Consequently, the voltage control signals control the delay produced by the delay gate array. This circuit is capable of precisely controlling the delay with a small number of elements and a small circuit scale.
摘要翻译：半导体集成电路具有电压发生器，延迟门阵列和电流控制器。电压发生器响应于电压控制信号产生输出电压。延迟门阵列具有用于产生延迟的级联延迟门。电流控制器响应于电压发生器的输出电压控制流向延迟门阵列的电流。因此，电压控制信号控制由延迟门阵列产生的延迟。该电路能够以少量的元件和小的电路规模精确地控制延迟。

98. 发明授权

US5715203A Semiconductor memory device and automatic bit line precharge method therefor 失效
标题翻译：半导体存储器件及其自动位线预充电方法
公开(公告)号：US5715203A
公开(公告)日：1998-02-03
申请号：US617073
申请日：1996-03-18
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/407 , G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C7/1072
摘要： The present invention relates to a semiconductor memory device having a bit line precharge circuit which precharges bit lines forming a data transfer path coupled to cells. The memory device is further provided with a first control circuit which controls the bit line precharge circuit to precharge the bit lines in response to a bit line precharge request, and a second control circuit which recognizes a command input from outside and makes the bit line precharge request with respect to the first control circuit. The second control circuit accepts a selection of whether or not to request automatic precharge of the bit lines when making an entry to a burst mode even when a burst length is set to a full column, and makes the bit line precharge request with respect to the first control circuit so that the bit lines are precharged after the burst mode ends when an entry to the burst mode requests the automatic precharge.
摘要翻译：本发明涉及一种具有位线预充电电路的半导体存储器件，该位线预充电电路对形成耦合到单元的数据传输路径的位线进行预充电。该存储装置还设置有第一控制电路，其控制位线预充电电路以响应于位线预充电请求对位线进行预充电;以及第二控制电路，其识别从外部输入的命令并使位线预充电关于第一控制电路的请求。第二控制电路即使当突发长度被设置为全列时也接受选择是否要在进入突发模式时请求位线的自动预充电，并且相对于第一控制电路，使得当突发模式的进入请求自动预充电时，突发模式结束之后，位线被预充电。

99. 发明授权

US5548437A Optical deflector provided with scanning mirror rotatable around shaft by dynamic air pressure 失效
标题翻译：光学偏转器设有扫描镜，通过动态空气压力可绕轴旋转
公开(公告)号：US5548437A
公开(公告)日：1996-08-20
申请号：US356894
申请日：1994-12-15
申请人： Shigeka Yoshimoto , Akiyoshi Takahashi , Toshiya Uchida , Rie Wakashima
发明人： Shigeka Yoshimoto , Akiyoshi Takahashi , Toshiya Uchida , Rie Wakashima
IPC分类号： G02B26/12 , G02B26/08
CPC分类号： G02B26/121
摘要： An optical deflector is provided with a scanning mirror which is rotatable about a shaft and accompanied by a sleeve and hub. The pneumatic pressure around the mirror which is located within a cavity formed by a motor case of the deflector is maintained lower than an inside pneumatic pressure of a pneumatic pressure creation arrangement. The arrangement has the shaft provided with herringbone grooves engraved on the periphery thereof and the sleeve rotatable about the shaft together with the hub and the scanning mirror. When the scanning mirror rotates about the shaft, windage loss may be reduced, and when the inside pneumatic pressure between the shaft and the sleeve is kept higher than the atmospheric pressure, the rigidity of the shaft may be maintained during the rotation of scanning mirror about the shaft.
摘要翻译：光学偏转器设有扫描镜，该扫描镜可围绕轴旋转并伴随着套筒和轮毂。位于由偏转器的电机壳形成的空腔内的反射镜周围的气动压力保持低于气动压力产生装置的内部气动压力。该装置具有设置有雕刻在其周边上的人字形槽的轴，并且套筒可与轮毂和扫描反射镜一起围绕轴旋转。当扫描镜绕轴旋转时，可能降低风阻损失，并且当轴和套筒之间的内部气动压力保持高于大气压力时，可以在扫描镜旋转期间保持轴的刚度约轴。

100. 发明授权

US5544109A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5544109A
公开(公告)日：1996-08-06
申请号：US205361
申请日：1994-03-03
申请人： Toshiya Uchida , Masao Taguchi
发明人： Toshiya Uchida , Masao Taguchi
IPC分类号： G11C11/417 , G11C7/10 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1048
摘要： A semiconductor memory device includes a flip-flop circuit, a switch provided between the flip-flop circuit and a pair of data lines, a write circuit writing data into the flip-flop circuit via the switch, and a circuit applying a predetermined voltage to the pair of data lines when the write circuit performs a write operation so that a voltage amplitude on the pair of data lines is limited so as to be less than a voltage amplitude of the flip-flop circuit in the write operation.
摘要翻译：半导体存储器件包括触发器电路，设置在触发器电路和一对数据线之间的开关，写入电路经由开关将数据写入触发器电路，以及将预定电压施加到当写入电路执行写入操作以使得该对数据线上的电压幅度被限制为小于写入操作中触发器电路的电压幅度时，该对数据线。

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