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91. 发明授权

US06833613B1 Stacked semiconductor package having laser machined contacts 有权
标题翻译：具有激光加工触点的堆叠半导体封装
公开(公告)号：US06833613B1
公开(公告)日：2004-12-21
申请号：US09961646
申请日：2001-09-25
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2302
CPC分类号： H01L24/81 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/48227 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the substrate adapted to electrically engage external contacts (e.g., bond pads, solder bumps) on the components. The interconnect also includes insulated conductive members through the substrate, which provide direct electrical paths from the interconnect contacts to a backside of the substrate. The conductive members can be formed by laser machining openings in the substrate, and then filling the openings with a conductive material (e.g., metal, conductive polymer). The conductive members can also include pads with contact balls, configured for electrical interface with a test apparatus, such as test carrier or wafer handler. The interconnect can be used to construct test systems for testing semiconductor components, or to construct chip scale packages and multi chip modules.
摘要翻译：提供了诸如骰子，晶片和芯片级封装的半导体元件的互连。互连包括衬底和形成在衬底的面侧上的触点图案，其适于电耦合组件上的外部触点（例如，接合焊盘，焊料凸块）。互连还包括通过衬底的绝缘导电构件，其提供从互连触点到衬底背面的直接电路径。导电构件可以通过在衬底中激光加工开口形成，然后用导电材料（例如金属，导电聚合物）填充开口。导电构件还可以包括具有接触球的焊盘，其被配置为与诸如测试载体或晶片处理器的测试装置电接口。互连可用于构建用于测试半导体元件的测试系统，或构建芯片级封装和多芯片模块。

92. 发明授权

US06815314B2 Hermetic chip and method of manufacture 失效
标题翻译：密封芯片和制造方法
公开(公告)号：US06815314B2
公开(公告)日：2004-11-09
申请号：US09923687
申请日：2001-08-06
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21306
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.

93. 发明授权

US06787888B2 High permeability composite films to reduce noise in high speed interconnects 失效
标题翻译：高磁导率复合薄膜可降低高速互连中的噪声
公开(公告)号：US06787888B2
公开(公告)日：2004-09-07
申请号：US10371009
申请日：2003-02-20
申请人： Leonard Forbes , Kie Y. Ahn , Salman Akram
发明人： Leonard Forbes , Kie Y. Ahn , Salman Akram
IPC分类号： H01L2906
CPC分类号： G11C7/02 , G11C7/18 , H01L23/5225 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H01L2924/00
摘要： A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.
摘要翻译：存储器件具有用于改善集成电路上的传输线操作的结构。用于传输线操作的结构包括在衬底上的第一层导电材料。第一层绝缘材料形成在导电材料的第一层上。在第一绝缘材料层上形成多个高磁导率金属线。高渗透性金属线的数量包括复合六铁氧体膜。多个传输线形成在绝缘材料的第一层上并且与多个高导磁率金属线之间并且平行。在传输线和高磁导率金属线上形成第二层绝缘材料。用于传输线操作的结构包括在第二绝缘材料层上的第二层导电材料。

94. 发明授权

US06785144B1 High density stackable and flexible substrate-based devices and systems and methods of fabricating 有权
标题翻译：高密度可堆叠和灵活的基于衬底的器件及其制造方法和制造方法
公开(公告)号：US06785144B1
公开(公告)日：2004-08-31
申请号：US09645373
申请日：2000-08-24
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： H05K706
CPC分类号： H05K1/147 , H01L23/5387 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/3011 , H05K1/141 , H05K1/144 , H05K1/189 , H05K2201/10674 , H05K2201/2018 , H01L2224/0401
摘要： A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.
摘要翻译：一种柔性载体衬底组件或模块，其有助于堆叠多个承载用于高密度电子系统的半导体晶片的载体衬底。在将骰子放置在柔性基板上之后，可以将柔性支撑框架施加到柔性基板上。支撑框架包括穿过其中的导电路径以连接到从衬底上的骰子延伸到衬底周边的电路迹线，以互连叠加的载体衬底。柔性载体基底可以弯曲到任何给定曲率的半径以符合各种非平面的规则和不规则表面。此外，由于框架以及基板可以是柔性的，多个柔性基板组件可以一个在另一个的顶部上堆叠，其中上部组件具有与下部模块不同的半径，并且任何中间组件具有从底部到最高职位。

95. 发明授权

US06760970B2 Method for forming modular sockets using flexible interconnects and resulting structures 失效
标题翻译：使用柔性互连和结构的结构形成模块化插座的方法
公开(公告)号：US06760970B2
公开(公告)日：2004-07-13
申请号：US10218334
申请日：2002-08-13
申请人： Warren M. Farnworth , David J. Corisis , Salman Akram
发明人： Warren M. Farnworth , David J. Corisis , Salman Akram
IPC分类号： H05K300
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06593 , H01L2924/0002 , H01L2924/3011 , H01R12/57 , H01R12/7082 , H01R12/721 , H01R12/856 , H01R13/24 , H01R13/514 , H05K7/023 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49169 , Y10T29/49204 , Y10T29/49222 , H01L2924/00
摘要： Methods for forming a modular bare die socket assembly 10 and attaching a plurality of miniature semiconductor dice 18 to a substrate. The socket assembly 10 is comprised of a plurality of two-sided plates 14 joined vertically in a horizontal stack, wherein each plate 14 has a die socket 22 for the removable insertion of a bare semiconductor die 18. A multi-layer interconnect lead tape 50 has a plurality of lithographically formed leads bent on one end to form nodes 88 for attachment to bond pads 90 on the removably inserted semiconductor die 18, and having opposing ends 92 connectable to the substrate.
摘要翻译：用于形成模块化裸模插座组件10并将多个微型半导体裸片18附接到衬底的方法。插座组件10由在水平叠层中垂直连接的多个双面板14组成，其中每个板14具有用于可裸插入裸半导体管芯18的管芯插座22.多层互连引线带50 具有在一端弯曲的多个光刻形成的引线以形成用于附接到可移除插入的半导体管芯18上的接合焊盘90的节点88，并且具有可连接到基板的相对端92。

96. 发明授权

US06758696B2 Method and apparatus for forming modular sockets using flexible interconnects and resulting structures 失效
标题翻译：用于使用柔性互连和结构的结构形成模块化插座的装置
公开(公告)号：US06758696B2
公开(公告)日：2004-07-06
申请号：US10401052
申请日：2003-03-27
申请人： Warren M. Farnworth , David J. Corisis , Salman Akram
发明人： Warren M. Farnworth , David J. Corisis , Salman Akram
IPC分类号： H01R2370
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06593 , H01L2924/0002 , H01L2924/3011 , H01R12/57 , H01R12/7082 , H01R12/721 , H01R12/856 , H01R13/24 , H01R13/514 , H05K7/023 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49169 , Y10T29/49204 , Y10T29/49222 , H01L2924/00
摘要： A modular bare die socket assembly for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a plurality of two-sided plates joined vertically in a horizontal stack, wherein each plate has a die socket for the removable insertion of a bare semiconductor die. A multi-layer interconnect lead tape has a plurality of lithographically formed leads bent on one end to form nodes for attachment to bond pads on the removably inserted semiconductor die, and having opposing ends connectable to the substrate.
摘要翻译：一种用于将多个微型半导体管芯附接到衬底的模块裸露裸露插座组件。插座组件由在水平叠层中垂直连接的多个双面板组成，其中每个板具有用于可裸插入裸半导体管芯的管芯插座。多层互连引线带具有在一端弯曲的多个光刻形成的引线，以形成用于附接到可移除插入的半导体管芯上的接合焊盘并具有可连接到基板的相对端的节点。

97. 发明授权

US06744346B1 Electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece 失效
公开(公告)号：US06744346B1
公开(公告)日：2004-06-01
申请号：US09032184
申请日：1998-02-27
申请人： Salman Akram , David R. Hembree
发明人： Salman Akram , David R. Hembree
IPC分类号： H01C304
CPC分类号： G01K1/026 , H01L22/12 , H01L2224/48091 , H01L2224/48464 , H01L2224/8592 , H01L2924/15156 , H01L2924/00014
摘要： The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention provides an electronic device workpiece including: a substrate having a surface; a temperature sensing device borne by the substrate; and an electrical interconnect formed upon the surface of the substrate, the electrical interconnect being electrically coupled with the temperature sensing device. In another aspect, a method of sensing temperature of an electronic device workpiece includes: providing an electronic device workpiece; supporting a temperature sensing device using the electronic device workpiece; providing an electrical interconnect upon a surface of the electronic device workpiece; electrically coupling the electrical interconnect with the temperature sensing device; and sensing temperature of the electronic device workpiece using the temperature sensing device.

98. 发明授权

US06740578B2 Methods of fabricating semiconductor substrate-based BGA interconnections 失效
公开(公告)号：US06740578B2
公开(公告)日：2004-05-25
申请号：US10310257
申请日：2002-12-04
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： H01L2144
CPC分类号： H01L23/49811 , G01R1/0408 , G01R1/0466 , G01R1/0483 , H01L24/12 , H01L2224/0401 , H01L2224/0603 , H01L2224/1403 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H05K1/112
摘要： The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately 10% to 50%, and preferably about 30%, of the total height of each solder ball within its associated interconnection. Such a design compensates for undersized or misshapen solder balls on the die under test and thereby prevents a possible false failure indication for the die under test. This design also distributes the forces on the solder ball caused by biasing the die under test to its temporary package to the periphery of the solder ball and thus reduces the likelihood of damage to the solder ball or the semiconductor substrate.

99. 发明授权

US06730526B2 Multi-chip module system and method of fabrication 失效
标题翻译：多芯片模块系统及其制造方法
公开(公告)号：US06730526B2
公开(公告)日：2004-05-04
申请号：US10033234
申请日：2001-12-28
申请人： Salman Akram , David R. Hembree , James M. Wark
发明人： Salman Akram , David R. Hembree , James M. Wark
IPC分类号： H01L2100
CPC分类号： H01L23/5382 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.
摘要翻译：多芯片模块系统及其制造方法，其中将多芯片模块（MCM）的故障芯片的等同物添加到先前用适当的电连接构造的空位中的模块中。各种不同的骰子可以通过适配器连接到MCM的相同空位，其中每个适配器具有相同的占位面积，但是不同的适配器能够容纳不同数量和类型的骰子。

100. 发明授权

US06696109B2 Chemical vapor deposition process for depositing titanium silicide films from an organometallic compound 有权
标题翻译：用于从有机金属化合物沉积硅化钛膜的化学气相沉积工艺
公开(公告)号：US06696109B2
公开(公告)日：2004-02-24
申请号：US10300327
申请日：2002-11-19
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： C23C1642
CPC分类号： C23C16/42
摘要： A process for depositing titanium silicide films via chemical vapor deposition takes place in a deposition chamber that has been evacuated to less than atmospheric pressure and utilizes, as reactants, the organometallic compound tertiary-butyltris-dimethylamido-titanium and a silicon-containing compound such as silane.
摘要翻译：通过化学气相沉积沉积硅化钛膜的方法发生在已被排空到小于大气压的沉积室中，并且作为反应物使用有机金属化合物叔丁基三 - 二甲基氨基 - 钛和含硅化合物，例如硅烷。

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