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91. 发明授权

US06815336B1 Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing 有权
标题翻译：使用反电流电镀和化学机械抛光对铜镶嵌进行平面化
公开(公告)号：US06815336B1
公开(公告)日：2004-11-09
申请号：US09160965
申请日：1998-09-25
申请人： Shau-Lin Shue , Syun-Ming Jang
发明人： Shau-Lin Shue , Syun-Ming Jang
IPC分类号： H01L214763
CPC分类号： H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/7684
摘要： Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet chemical etching, stripping the photo resist, and a subsequent chemical mechanical planarization of the copper damascene. Lastly a cap layer is applied to the planarized surface. In a variant of the disclosed method a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use. These steps provide benefits such as improved uniformity of the wafer surface, reduce the dishing of metal lines (trenches) and pads, and reduce oxide erosion.
摘要翻译：公开了通过以下步骤来改善铜镶嵌的平面化的步骤：使用反色调光掩模或金属线的反色调光掩模在铜镶嵌光致抗蚀剂上进行图案化，通过反向电镀或通过干或湿去除多余的铜化学蚀刻，剥离光致抗蚀剂，以及铜镶嵌件的随后的化学机械平面化。最后，将覆盖层施加到平坦化表面。在所公开的方法的变型中，使用金属线的更宽松的反向色调光掩模，这对于实际使用可能是更理想的。这些步骤提供了诸如改善晶片表面的均匀性，减少金属线（沟槽）和焊盘的凹陷以及减少氧化物侵蚀的益处。

92. 发明授权

US06812069B2 Method for improving semiconductor process wafer CMP uniformity while avoiding fracture 失效
$Method for improving semiconductor process wafer CMP uniformity while avoiding fracture$
标题翻译：改善半导体工艺晶片CMP均匀性同时避免断裂的方法
公开(公告)号：US06812069B2
公开(公告)日：2004-11-02
申请号：US10322691
申请日：2002-12-17
申请人： Tung-Ching Tseng , Syun-Ming Jang , Chih-Hsiang Yao
发明人： Tung-Ching Tseng , Syun-Ming Jang , Chih-Hsiang Yao
IPC分类号： H01L2182
CPC分类号： H01L21/7684 , H01L21/3212 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.
摘要翻译：一种通过减少与虚拟特征相邻的应力集中来提高CMP抛光均匀性并减少或防止半导体晶片工艺表面中的裂纹的方法，包括提供半导体晶片工艺表面，其包括与活性特征相邻形成的活性特征和虚拟特征，以改善CMP抛光均匀性，所述虚拟特征各自被成形为在包括至少5个角部的所述半导体晶片工艺表面中限定封闭区域; 以及在所述半导体晶片处理表面上执行CMP处理。

93. 发明授权

US06812043B2 Method for forming a carbon doped oxide low-k insulating layer 有权
标题翻译：形成碳掺杂氧化物低k绝缘层的方法
公开(公告)号：US06812043B2
公开(公告)日：2004-11-02
申请号：US10131713
申请日：2002-04-25
申请人： Tien-I Bao , Chung-Chi Ko , Lih-Ping Li , Syun-Ming Jang
发明人： Tien-I Bao , Chung-Chi Ko , Lih-Ping Li , Syun-Ming Jang
IPC分类号： H01L2100
CPC分类号： H01L21/76826 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/31633 , H01L21/76807
摘要： A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.
摘要翻译：一种用于半导体器件制造的具有降低的介电常数和增加的硬度的介电绝缘层的形成方法，包括提供具有在其上形成电介质绝缘层的工艺表面的半导体晶片; 根据CVD工艺沉积碳掺杂氧化物层的CVD工艺，其包括具有Si-O基团和Si-Ry基团的牛至硅烷前体，其中R是烷基或环烷基，y是与硅; 并且将碳掺杂的氧化物层暴露于氢等离子体处理一段时间，从而减少碳掺杂的氧化物层厚度，包括减少碳掺杂的氧化物层介电常数并增加碳掺杂的氧化物层的硬度。

94. 发明授权

US06559040B1 Process for polishing the top surface of a polysilicon gate 有权
标题翻译：抛光多晶硅栅极顶表面的工艺
公开(公告)号：US06559040B1
公开(公告)日：2003-05-06
申请号：US09421517
申请日：1999-10-20
申请人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
发明人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , H01L21/28035
摘要： The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.
摘要翻译：抛光多晶硅栅电极的顶表面的过程通常在达到足够的平滑度之前导致材料的显着损失。在本发明中通过在施加CMP之前在多晶硅的表面上放置介电层的薄层来克服该问题。这提供了促进抛光操作的牺牲层，并且导致多晶硅表面非常平滑并且可以以最小的多晶硅损失实现。

95. 发明授权

US06479385B1 Interlevel dielectric composite layer for insulation of polysilicon and metal structures 有权
标题翻译：用于多晶硅和金属结构绝缘的层间电介质复合层
公开(公告)号：US06479385B1
公开(公告)日：2002-11-12
申请号：US09583397
申请日：2000-05-31
申请人： Syun-Ming Jang , Chu-Yun Fu
发明人： Syun-Ming Jang , Chu-Yun Fu
IPC分类号： H01L21302
CPC分类号： H01L21/02238 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02255 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/31625 , H01L21/76801 , H01L21/76837
摘要： A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.
摘要翻译：已经开发了用于形成MOSFET器件的复合层间电介质（ILD）层的工艺。复合ILD层包含底层的未掺杂的硅玻璃层，提供填充MOSFET器件的多晶硅栅极结构之间的狭窄空间所需的材料。随后在下面未掺杂的硅玻璃层上形成P2O5掺杂的绝缘体层，以提供移动离子吸杂性质。然后沉积覆盖的未掺杂的硅玻璃层，并进行化学机械抛光程序，得到复合ILD层所需的平面顶表面形貌。

96. 发明授权

US06458689B2 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE氧化物进行接触或通过照相和氧化物和化学机械抛光剂进行缺陷还原
公开(公告)号：US06458689B2
公开(公告)日：2002-10-01
申请号：US09818714
申请日：2001-03-28
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介质层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在电介质层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

97. 发明授权

US06424038B1 Low dielectric constant microelectronic conductor structure with enhanced adhesion and attenuated electrical leakage 有权
标题翻译：低介电常数微电子导体结构具有增强的附着力和减弱的漏电
公开(公告)号：US06424038B1
公开(公告)日：2002-07-23
申请号：US09812029
申请日：2001-03-19
申请人： Tien-I Bao , Syun-Ming Jang
发明人： Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/7681 , H01L23/3192 , H01L23/49894 , H01L23/53238 , H01L23/53271 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： Within both a microelectronic conductor structure and a method for forming the microelectronic conductor structure there is employed a silicon carbide layer having formed thereupon a silicon nitride layer in turn having formed thereupon a patterned low dielectric constant dielectric layer in turn having formed interposed between its patterns a patterned conductor layer. Within both the microelectronic conductor structure and the method for forming the microelectronic conductor structure, by employing the silicon carbide layer having formed thereupon the silicon nitride layer in turn having formed thereupon the patterned low dielectric constant dielectric layer, the microelectronic conductor structure is formed with enhanced adhesion and attenuated electrical leakage.
摘要翻译：在微电子导体结构和形成微电子导体结构的方法中，都采用在其上形成氮化硅层的碳化硅层，依次形成图案化的低介电常数介电层，其间形成有介于其图案a 图案导体层。在微电子导体结构和形成微电子导体结构的方法中，通过使用其上形成的碳化硅层依次形成有图案化的低介电常数介电层的氮化硅层，微电子导体结构形成有增强的粘附和减弱漏电。

98. 发明授权

US06391792B1 Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer 有权
标题翻译：用于形成图案化平面化孔径填充层的多步化学机械抛光（CMP）平面化方法
公开(公告)号：US06391792B1
公开(公告)日：2002-05-21
申请号：US09573981
申请日：2000-05-18
申请人： Syun-Ming Jang , Juing-Yi Cheng , Chung-Long Chang
发明人： Syun-Ming Jang , Juing-Yi Cheng , Chung-Long Chang
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Within a method for forming an aperture fill layer within a aperture, there is first provided a topographic substrate having an aperture formed therein. There is then formed over the topographic substrate and filling the aperture a blanket aperture fill layer. There is then planarized, while employing a first chemical mechanical polish (CMP) planarizing method, the blanket aperture fill layer to form a blanket planarized aperture fill layer while not reaching the topographic substrate. Finally, there is then planarized, while employing a second planarizing method, the blanket planarized aperture fill layer to form within the aperture a patterned planarized aperture fill layer. The two step planarizing method may be employed for forming with enhanced planarity and attenuated topographic substrate erosion a patterned planarized aperture fill layer, such as a patterned planarized trench isolation region, within a topographic substrate, such as a topographic semiconductor substrate.
摘要翻译：在用于在孔内形成孔填充层的方法中，首先提供其中形成有孔的形貌基底。然后形成在地形衬底上并且将孔填充到覆盖孔填充层。然后平面化，同时采用第一化学机械抛光（CMP）平面化方法，橡皮布孔填充层，以形成覆盖平面化的孔填充层，同时不能到达地形衬底。最后，在采用第二平面化方法的同时平面化平坦化的平面化孔径填充层，以在孔内形成图案化的平坦化孔填充层。可以采用两步平面化方法来形成具有增强的平面度和衰减的地形衬底侵蚀的图案化的平坦化孔填充层，例如图形化的平面化沟槽隔离区域，在地形衬底（例如地形半导体衬底）内。

99. 发明授权

US06350694B1 Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials 有权
标题翻译：对于低k材料，通过后CMP回蚀法减少CMP划痕，凹陷和侵蚀
公开(公告)号：US06350694B1
公开(公告)日：2002-02-26
申请号：US09814038
申请日：2001-03-22
申请人： Weng Chang , Tien-I Bao , Syun-Ming Jang
发明人： Weng Chang , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40603 , G11C11/4096 , H01L21/02074 , H01L21/31055 , H01L21/31058 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.
摘要翻译：提供了一种新的等离子体回蚀，其在铜表面的CMP处理已经完成之后被施加到低k电介质的表面。铜表面是互连金属的表面，互连金属嵌入在低k电介质层中。

100. 发明授权

US06316348B1 High selectivity Si-rich SiON etch-stop layer 有权
标题翻译：高选择性富硅SiON蚀刻停止层
公开(公告)号：US06316348B1
公开(公告)日：2001-11-13
申请号：US09838627
申请日：2001-04-20
申请人： Chu Yun Fu , Chia Shiung Tsai , Syun-Ming Jang
发明人： Chu Yun Fu , Chia Shiung Tsai , Syun-Ming Jang
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/31116 , H01L21/3144 , H01L21/3145 , H01L21/76801 , H01L21/7681 , H01L21/76813
摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynnitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.
摘要翻译：本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并且可用作多晶硅栅极上的硬掩模。本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。在第一绝缘层中蚀刻第一开口。第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。第二个双镶嵌开口被蚀刻到电介质层中。在这些操作期间，抗反射Si富硅氧氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的变形。

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