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1. 发明授权

US06815336B1 Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing 有权
标题翻译：使用反电流电镀和化学机械抛光对铜镶嵌进行平面化
公开(公告)号：US06815336B1
公开(公告)日：2004-11-09
申请号：US09160965
申请日：1998-09-25
申请人： Shau-Lin Shue , Syun-Ming Jang
发明人： Shau-Lin Shue , Syun-Ming Jang
IPC分类号： H01L214763
CPC分类号： H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/7684
摘要： Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet chemical etching, stripping the photo resist, and a subsequent chemical mechanical planarization of the copper damascene. Lastly a cap layer is applied to the planarized surface. In a variant of the disclosed method a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use. These steps provide benefits such as improved uniformity of the wafer surface, reduce the dishing of metal lines (trenches) and pads, and reduce oxide erosion.
摘要翻译：公开了通过以下步骤来改善铜镶嵌的平面化的步骤：使用反色调光掩模或金属线的反色调光掩模在铜镶嵌光致抗蚀剂上进行图案化，通过反向电镀或通过干或湿去除多余的铜化学蚀刻，剥离光致抗蚀剂，以及铜镶嵌件的随后的化学机械平面化。最后，将覆盖层施加到平坦化表面。在所公开的方法的变型中，使用金属线的更宽松的反向色调光掩模，这对于实际使用可能是更理想的。这些步骤提供了诸如改善晶片表面的均匀性，减少金属线（沟槽）和焊盘的凹陷以及减少氧化物侵蚀的益处。

2. 发明授权

US06620725B1 Reduction of Cu line damage by two-step CMP 有权
标题翻译：通过两步CMP减少Cu线损伤
公开(公告)号：US06620725B1
公开(公告)日：2003-09-16
申请号：US09395287
申请日：1999-09-13
申请人： Shau-Lin Shue , Ming-Hsing Tsai , Wen-Jye Tsai , Ying-Ho Chen , Tsu Shih , Jih-Churng Twu , Syun-Ming Jang
发明人： Shau-Lin Shue , Ming-Hsing Tsai , Wen-Jye Tsai , Ying-Ho Chen , Tsu Shih , Jih-Churng Twu , Syun-Ming Jang
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.
摘要翻译：描述用于在两个步骤中执行CMP的过程。在沟槽已经形成并且用铜过度填充之后，在本发明的第一实施例中，最初使用硬焊盘去除大部分铜，直到达到一个点，其中凹陷效应将开始出现。然后取代软焊盘，继续CMP直到除了沟槽中除去所有的铜。在第二实施例中，使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。如前所述，使用这种组合，直到达到点，其中凹陷效应将开始出现。然后，除了沟槽之外，使用相对较低的压力结合相对高的转速直到除去所有的铜。这两个实施例都导致刚好填充铜的沟槽，几乎没有凹陷效应，并且除了沟槽本身之外，所有痕迹的铜都被去除。

3. 发明授权

US06736701B1 Eliminate broken line damage of copper after CMP 失效
标题翻译：消除CMP后的铜线损伤
公开(公告)号：US06736701B1
公开(公告)日：2004-05-18
申请号：US09989838
申请日：2001-11-20
申请人： Shau-Lin Shue , Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
发明人： Shau-Lin Shue , Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
IPC分类号： B24B100
CPC分类号： B24B37/042 , B24B21/04
摘要： A new method is provided for the post-deposition treatment of copper lines. A damascene copper line pattern whereby a TaN barrier layer and a seed layer have been provided is polished. Under the first embodiment of the invention, the deposited copper is polished (Cu CMP), the surface of the wafer is rinsed using a first High Flow DI rinse that contains a TBA inhibitor. The TaN CMP is performed immediately following the first High Flow DI rinse. A second High Flow DI rinse is applied using DI water that contains TBA inhibitor. The required following rinse step is executed immediately after the second High Flow DI rinse has been completed. Under the second embodiment of the invention, the process of CMP has been divided in two distinct steps where the first step is aimed at corrosion elimination and the second step is aimed at elimination of mechanical damage to the polished copper. The processing conditions for the second processing step have been extended and optimized, thereby using a second belt of a CMP apparatus.
摘要翻译：提供了一种新的铜线后处理方法。抛光已经提供TaN阻挡层和种子层的镶嵌铜线图案。在本发明的第一实施例中，抛光沉积的铜（Cu CMP），使用含有TBA抑制剂的第一高流量DI冲洗冲洗晶片的表面。在第一次高流量DI冲洗之后立即执行TaN CMP。使用含有TBA抑制剂的去离子水进行第二次高流量DI冲洗。第二次高流量DI冲洗完成后立即执行所需的冲洗步骤。在本发明的第二个实施方案中，CMP的方法分为两个不同的步骤，其中第一步骤旨在消除腐蚀，第二步骤旨在消除抛光铜的机械损伤。第二处理步骤的处理条件已被扩展和优化，从而使用CMP设备的第二带。

4. 发明授权

US06277745B1 Passivation method of post copper dry etching 有权
标题翻译：后铜干蚀刻钝化法
公开(公告)号：US06277745B1
公开(公告)日：2001-08-21
申请号：US09221965
申请日：1998-12-28
申请人： Chung-Shi Liu , Shau-Lin Shue , Syun-Ming Jang , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/02071 , H01L21/321 , H01L21/32136 , H01L21/76841 , H01L21/7685 , H01L21/76852 , H01L21/76885
摘要： The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines after they have been patterned by a dry etch process. The method includes the formation of a sandwich structure consisting of a bottom barrier layer, a copper layer and a top barrier layer. After the sandwich structure is patterned with a dry etch, for example, the resultant exposed copper sidewalls are then passivated by means of a barrier metal spacer process. The fully encapsulated copper lines are highly resistant to oxidation, which is an, otherwise, inherent problem associated with the lack of self passivation/exhibited by bare copper films.
摘要翻译：本发明涉及用于半导体工业的铜电互连钝化的新结构和方法。更具体地，本发明详细描述了在通过干蚀刻工艺对其进行图案化之后完成铜线钝化的方便方法。该方法包括形成由底部阻挡层，铜层和顶部阻挡层组成的夹层结构。在用干蚀刻图案化夹层结构之后，然后通过阻挡金属间隔物工艺钝化所得到的暴露的铜侧壁。完全封装的铜线具有很高的抗氧化性，这是另一种与裸铜膜缺乏自钝化/显示相关的固有问题。

5. 发明授权

US09647066B2 Dummy FinFET structure and method of making same 有权
公开(公告)号：US09647066B2
公开(公告)日：2017-05-09
申请号：US13454960
申请日：2012-04-24
申请人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
发明人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
IPC分类号： H01L27/088 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/20
CPC分类号： H01L29/10 , H01L21/823431 , H01L27/0886 , H01L29/6681 , H01L29/785
摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

6. 发明授权

US09269612B2 Mechanisms of forming damascene interconnect structures 有权
标题翻译：形成镶嵌互连结构的机制
公开(公告)号：US09269612B2
公开(公告)日：2016-02-23
申请号：US13434691
申请日：2012-03-29
申请人： Chien-An Chen , Wen-Jiun Liu , Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
发明人： Chien-An Chen , Wen-Jiun Liu , Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76819 , H01L21/76834 , H01L21/76843 , H01L21/76847 , H01L21/76849 , H01L21/7685 , H01L21/76864 , H01L21/76882 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.
摘要翻译：互连结构包括第一沟槽和第二沟槽。第二沟槽比第一沟槽宽。这两个沟槽都带有扩散阻挡层，并且第一导电层沉积在扩散阻挡层上。在第一导电层上沉积金属覆盖层。第二导电层沉积在第二沟槽中的金属覆盖层上。

7. 发明授权

US09029260B2 Gap filling method for dual damascene process 有权
标题翻译：双镶嵌工艺的间隙填充方法
公开(公告)号：US09029260B2
公开(公告)日：2015-05-12
申请号：US13161701
申请日：2011-06-16
申请人： Chun Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
发明人： Chun Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/44 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/7681 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L29/511 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括形成具有多个第一开口的图案化电介质层。该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。该方法包括去除沟槽掩模层。

8. 发明授权

US08932962B2 Chemical dispensing system and method 有权
标题翻译：化学分配系统和方法
公开(公告)号：US08932962B2
公开(公告)日：2015-01-13
申请号：US13442040
申请日：2012-04-09
申请人： Weibo Yu , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/302
CPC分类号： H01L21/6708 , H01L21/30608 , H01L21/31111 , H01L21/67109 , H01L22/12 , H01L22/20
摘要： A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.
摘要翻译：用于将液体蚀刻剂分配到晶片上的方法和设备使用扫描分配喷嘴将液体蚀刻剂分配到晶片上，同时根据分配喷嘴在晶片上的径向位置实时控制蚀刻剂的分配温度。控制蚀刻剂的分配温度以提高蚀刻剂的有效性，从而补偿晶片中较低的蚀刻速率区域。

9. 发明授权

US08609484B2 Method for forming high-K metal gate device 有权
标题翻译：用于形成高K金属栅极器件的方法
公开(公告)号：US08609484B2
公开(公告)日：2013-12-17
申请号：US12617004
申请日：2009-11-12
申请人： Lee-Wee Tao , Han-Guan Chew , Harry Hak-Lay Chuang , Syun-Ming Jang
发明人： Lee-Wee Tao , Han-Guan Chew , Harry Hak-Lay Chuang , Syun-Ming Jang
IPC分类号： H01L29/00
CPC分类号： H01L29/7845 , H01L21/28518 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成金属栅极，具有第一栅极电阻的金属栅极，去除金属栅极的一部分从而形成沟槽; 以及在所述沟槽内形成导电结构，使得所述导电结构的第二栅极电阻和所述金属栅极的剩余部分低于所述第一栅极电阻。

10. 发明申请

US20130157462A1 METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20130157462A1
公开(公告)日：2013-06-20
申请号：US13328680
申请日：2011-12-16
申请人： Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai , Syun-Ming Jang
发明人： Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/28 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32
摘要： The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

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