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1. 发明授权

US06391792B1 Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer 有权
标题翻译：用于形成图案化平面化孔径填充层的多步化学机械抛光（CMP）平面化方法
公开(公告)号：US06391792B1
公开(公告)日：2002-05-21
申请号：US09573981
申请日：2000-05-18
申请人： Syun-Ming Jang , Juing-Yi Cheng , Chung-Long Chang
发明人： Syun-Ming Jang , Juing-Yi Cheng , Chung-Long Chang
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Within a method for forming an aperture fill layer within a aperture, there is first provided a topographic substrate having an aperture formed therein. There is then formed over the topographic substrate and filling the aperture a blanket aperture fill layer. There is then planarized, while employing a first chemical mechanical polish (CMP) planarizing method, the blanket aperture fill layer to form a blanket planarized aperture fill layer while not reaching the topographic substrate. Finally, there is then planarized, while employing a second planarizing method, the blanket planarized aperture fill layer to form within the aperture a patterned planarized aperture fill layer. The two step planarizing method may be employed for forming with enhanced planarity and attenuated topographic substrate erosion a patterned planarized aperture fill layer, such as a patterned planarized trench isolation region, within a topographic substrate, such as a topographic semiconductor substrate.
摘要翻译：在用于在孔内形成孔填充层的方法中，首先提供其中形成有孔的形貌基底。然后形成在地形衬底上并且将孔填充到覆盖孔填充层。然后平面化，同时采用第一化学机械抛光（CMP）平面化方法，橡皮布孔填充层，以形成覆盖平面化的孔填充层，同时不能到达地形衬底。最后，在采用第二平面化方法的同时平面化平坦化的平面化孔径填充层，以在孔内形成图案化的平坦化孔填充层。可以采用两步平面化方法来形成具有增强的平面度和衰减的地形衬底侵蚀的图案化的平坦化孔填充层，例如图形化的平面化沟槽隔离区域，在地形衬底（例如地形半导体衬底）内。

2. 发明授权

US06559040B1 Process for polishing the top surface of a polysilicon gate 有权
标题翻译：抛光多晶硅栅极顶表面的工艺
公开(公告)号：US06559040B1
公开(公告)日：2003-05-06
申请号：US09421517
申请日：1999-10-20
申请人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
发明人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , H01L21/28035
摘要： The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.
摘要翻译：抛光多晶硅栅电极的顶表面的过程通常在达到足够的平滑度之前导致材料的显着损失。在本发明中通过在施加CMP之前在多晶硅的表面上放置介电层的薄层来克服该问题。这提供了促进抛光操作的牺牲层，并且导致多晶硅表面非常平滑并且可以以最小的多晶硅损失实现。

3. 发明授权

US06207483B1 Method for smoothing polysilicon gate structures in CMOS devices 有权
标题翻译： CMOS器件中多晶硅栅极结构平滑化的方法
公开(公告)号：US06207483B1
公开(公告)日：2001-03-27
申请号：US09527183
申请日：2000-03-17
申请人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
发明人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
IPC分类号： H01L218238
CPC分类号： H01L21/823828 , H01L21/28035 , H01L21/32115
摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.
摘要翻译：提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。

4. 发明授权

US06444371B1 Prevention of die loss to chemical mechanical polishing 有权
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US06444371B1
公开(公告)日：2002-09-03
申请号：US09377541
申请日：1999-08-19
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

5. 发明授权

US6153512A Process to improve adhesion of HSQ to underlying materials 有权
标题翻译：提高HSQ与下层材料粘附性的工艺
公开(公告)号：US6153512A
公开(公告)日：2000-11-28
申请号：US414922
申请日：1999-10-12
申请人： Chung-Long Chang , Syun-Ming Jang
发明人： Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/02134 , H01L21/02131 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02282 , H01L21/02315 , H01L21/31058 , H01L21/3124 , H01L21/31629 , H01L21/76801 , H01L21/76826 , H01L21/76834
摘要： A process for forming an intermetal dielectric, (IMD), layer, comprised of an overlying silicon oxide layer, and an underlying low k dielectric layer, such as hydrogen silsesquioxane, (HSQ), has been developed. The process features the use of a series of plasma treatments, performed in a nitrogen containing ambient, used to improve the adhesion of the IMD layer, to underlying materials. A first plasma treatment is performed on a thin insulator layer, prior to application of the HSQ layer. The plasma treatment roughens the top surface of the thin insulator layer, resulting in improved adhesion of the HSQ layer to the thin insulator layer. A second plasma treatment is performed to the HSQ layer, prior to deposition of the overlying, thick silicon oxide layer, allowing improve adhesion of the thick silicon oxide layer, to the underlying HSQ layer, to be achieved.
摘要翻译：已经开发了用于形成由上覆硅氧化物层构成的金属间电介质（IMD）层，和诸如氢倍半硅氧烷（HSQ）等下面的低k电介质层的工艺。该方法的特征在于使用一系列等离子体处理，其在含氮环境中进行，用于改善IMD层的附着力到下面的材料。在施加HSQ层之前，在薄绝缘体层上进行第一等离子体处理。等离子体处理使薄绝缘体层的顶表面变粗糙，从而改善了HSQ层与薄绝缘体层的粘合性。在沉积上覆的厚的氧化硅层之前，对HSQ层进行第二等离子体处理，以使得能够实现厚的氧化硅层与底层的HSQ层的粘附。

6. 发明授权

US06524906B2 Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer 有权
标题翻译：使用氮化硅阻挡层对多晶硅塞进行化学机械抛光
公开(公告)号：US06524906B2
公开(公告)日：2003-02-25
申请号：US09774416
申请日：2001-02-01
申请人： Syun-Ming Jang , Chung-Long Chang
发明人： Syun-Ming Jang , Chung-Long Chang
IPC分类号： H01L218242
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76819 , H01L27/10855 , H01L27/10888
摘要： A method for controllably simultaneously polishing polysilicon and oxide using an oxide slurry and a polish stop layer over the oxide is described. Semiconductor device structures are provided in and on a semiconductor substrate. An oxide layer is deposited overlying the semiconductor device structures. A silicon nitride layer is deposited overlying the oxide layer as a polish stop layer. A contact opening is etched through the silicon nitride layer and the oxide layer to one of the semiconductor device structures. A polysilicon layer is deposited overlying the silicon nitride layer and within the contact opening. The polysilicon layer is polished until the silicon nitride layer is contacted and then the polysilicon layer, silicon nitride layer, and oxide layer are overpolished in a timed polish to remove the silicon nitride layer and planarize the oxide layer to complete simultaneous planarization of the oxide and polysilicon layers in the fabrication of an integrated circuit device.
摘要翻译：描述了使用氧化物浆料和氧化物上的抛光停止层可控地同时研磨多晶硅和氧化物的方法。半导体器件结构设置在半导体衬底中和半导体衬底上。沉积覆盖在半导体器件结构上的氧化物层。沉积氮化硅层作为抛光停止层覆盖在氧化物层上。通过氮化硅层和氧化物层蚀刻接触开口到半导体器件结构之一。覆盖氮化硅层并且在接触开口内沉积多晶硅层。抛光多晶硅层直到氮化硅层接触，然后在定时抛光中对多晶硅层，氮化硅层和氧化物层进行过度抛光以去除氮化硅层并平坦化氧化物层以完成氧化物的同时平坦化，多晶硅层制造集成电路器件。

7. 发明授权

US06271123B1 Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG 失效
标题翻译：使用未掺杂的硅玻璃停止层进行抛光BPSG的化学机械抛光方法
公开(公告)号：US06271123B1
公开(公告)日：2001-08-07
申请号：US09086769
申请日：1998-05-29
申请人： Syun-Ming Jang , Chung-Long Chang
发明人： Syun-Ming Jang , Chung-Long Chang
IPC分类号： H01L2144
CPC分类号： H01L21/76819
摘要： A method using chemical-mechanical polishing for planarizing a BPSG layer 30 using a overlying Undoped Silicate Glass (USG) cap layer 40 comprising: (a) form a BPSG layer 30 over the semiconductor structure 12; the BPSG layer 30 over the periphery area 16 having a first thickness; (b) form a cap layer 40 composed of undoped silicon glass (USG) over the BPSG layer 30; the cap layer has a thickness that is at less than half of the first thickness of the BPSG layer; the top surface of the cap layer 40 in the cell area 14 is higher than the top surface of the BPSG layer 30 in the periphery area 16; (c) chemical-mechanical polish the cap layer 40 and the BPSG layer 30 over the cell area using the cap layer 40 over the periphery area 16 to retard the chemical-mechanical polish process when the top surface of the BPSG layer 30 over the cell area 14 is even with the cap layer 40 over the periphery area 16; and the cap layer 40 remains over the Periphery area 16.
摘要翻译：一种使用化学机械抛光的方法，其使用覆盖的未掺杂硅酸盐玻璃（USG）覆盖层40平坦化BPSG层30，其包括：（a）在半导体结构12上形成BPSG层30; BPSG层30在周边区域16上具有第一厚度;（b）在BPSG层30上形成由未掺杂的硅玻璃（USG）组成的覆盖层40; 盖层的厚度小于BPSG层的第一厚度的一半; 电池区域14中的盖层40的顶表面比周边区域16中的BPSG层30的顶表面高;（c）在电池区域上对盖层40和BPSG层30进行化学机械抛光当外壳区域16上的BPSG层30的顶表面在外围区域16上方具有盖层40时，使用边缘区域16上的覆盖层40来延迟化学机械抛光过程; 并且盖层40保留在周边区域16上。

8. 发明授权

US06242356B1 Etchback method for forming microelectronic layer with enhanced surface smoothness 有权
标题翻译：用于形成具有增强的表面光滑度的微电子层的Etchback方法
公开(公告)号：US06242356B1
公开(公告)日：2001-06-05
申请号：US09465230
申请日：1999-12-17
申请人： Syun-Ming Jang , Chung-Long Chang , Shwangming Jeng , Chen-Hua Yu
发明人： Syun-Ming Jang , Chung-Long Chang , Shwangming Jeng , Chen-Hua Yu
IPC分类号： H01L21311
CPC分类号： H01L21/28123 , H01L21/28035 , H01L21/28525 , H01L21/32115
摘要： A method for forming a microelectronic layer within a microelectronic fabrication first employs a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial smoothing layer. Finally, there is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with an enhanced surface smoothness in comparison with the target microelectronic layer.
摘要翻译：在微电子制造中形成微电子层的方法首先采用衬底。然后在衬底上形成目标微电子层。然后在目标微电子层上形成牺牲平滑层。最后，从目标微电子层完全蚀刻牺牲平滑层，同时与目标微电子层相比，部分蚀刻目标微电子层以形成具有增强的表面光滑度的部分蚀刻的目标微电子层。

9. 发明授权

US06191039B1 Method of CMP of polysilicon 有权
标题翻译：多晶硅的CMP方法
公开(公告)号：US06191039B1
公开(公告)日：2001-02-20
申请号：US09186390
申请日：1998-11-05
申请人： Chung-Long Chang , Syun-Ming Jang
发明人： Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , C09G1/02 , Y10S438/959
摘要： An improved and new process for fabricating a planarized structure of polysilicon plugs, embedded in silicon oxide has been developed. The planarizing method comprises a two-step CMP process in which the first. CMP step comprises chemical-mechanical polishing using a first polishing slurry which is selective to polysilicon and the second CMP step comprises chemical-mechanical polishing using a second polishing slurry which polishes both polysilicon and silicon oxide. The processing time of the two-step CMP process is significantly less than the processing time of a one-step CMP process requiring an over-polish period. This reduced processing time reduces the cost of the CMP operation and at the same time produces a product with superior planarity and without reliability degradation due to residues of polysilicon.
摘要翻译：已经开发了一种用于制造嵌入在氧化硅中的多晶硅插塞的平面化结构的改进和新工艺。平面化方法包括两步CMP工艺，其中第一步。 CMP步骤包括使用对多晶硅有选择性的第一抛光浆料进行化学机械抛光，并且第二CMP步骤包括使用抛光多晶硅和氧化硅两者的第二抛光浆料的化学机械抛光。两步CMP工艺的处理时间显着小于需要过抛光时间的一步CMP工艺的处理时间。这减少了处理时间，降低了CMP操作的成本，并且同时产生了由于多晶硅残留而具有优异的平面性和不可靠性劣化的产品。

10. 发明授权

US06176141B1 Method for stud pull test for film formed on semiconductor device 有权
标题翻译：半导体器件上形成的薄膜螺柱拉拔试验方法
公开(公告)号：US06176141B1
公开(公告)日：2001-01-23
申请号：US09332379
申请日：1999-06-14
申请人： Lung-Hsiang Chuang , Chung-Long Chang , Syun-Ming Jang , Ying-Chen Chao
发明人： Lung-Hsiang Chuang , Chung-Long Chang , Syun-Ming Jang , Ying-Chen Chao
IPC分类号： G01N300
CPC分类号： G01N3/00 , G01N19/04 , G01N2203/0017 , G01N2203/0091 , G01N2203/0282 , G01N2203/0286 , G01N2203/0296 , G01N2203/0429
摘要： A test sample with a film and an underlying substrate representing part of a semiconductor wafer is prepared for a stud pull test by a process that includes maintaining the sample in boiling salt water for a few hours. When an epoxy stud is attached to the film of the sample and the clamped assembly is baked for a about an hour, the stud is firmly attached to the film and in an otherwise conventional pull test, the film breaks loose from the substrate (or the stud breaks from the epoxy) before the stud breaks from the film.
摘要翻译：制备具有膜和表示半导体晶片的一部分的底层基板的测试样品用于通过包括将样品保持在沸腾的盐水中几个小时的方法进行螺柱拉拔测试。当将环氧树脂柱连接到样品的膜上并且夹持的组件烘烤约1小时时，螺柱牢固地附接到膜上，并且以其它常规的拉伸试验，膜从基板（或在螺柱从胶片上脱落之前，螺柱与环氧树脂断裂。

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