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91. 发明申请

US20070054489A1 Interconnect structures with encasing cap and methods of making thereof 失效
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US20070054489A1
公开(公告)日：2007-03-08
申请号：US11503259
申请日：2006-08-14
申请人： Kwong Wong , Louis Hsu , Timothy Dalton , Carl Radens , Chih-Chao Yang , Lawrence Clevenger , Theodorus Standaert
发明人： Kwong Wong , Louis Hsu , Timothy Dalton , Carl Radens , Chih-Chao Yang , Lawrence Clevenger , Theodorus Standaert
IPC分类号： H01L21/44
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，包括在电介质材料中提供互连结构，使电介质材料凹陷，使得互连结构的一部分在电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

92. 发明申请

US20060292852A1 BACK END INTERCONNECT WITH A SHAPED INTERFACE 失效
标题翻译：后端互连与形状接口
公开(公告)号：US20060292852A1
公开(公告)日：2006-12-28
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

93. 发明授权

US07102232B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

94. 发明授权

US07091612B2 Dual damascene structure and method 有权
公开(公告)号：US07091612B2
公开(公告)日：2006-08-15
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L23/12 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

95. 发明申请

US20060145792A1 STRUCTURE AND METHOD OF FABRICATING A HINGE TYPE MEMS SWITCH 有权
标题翻译：铰链类型MEMS开关的结构和方法
公开(公告)号：US20060145792A1
公开(公告)日：2006-07-06
申请号：US10905449
申请日：2005-01-05
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.
摘要翻译：描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松动地连接到引导柱; 上下电极对; 以及由可动导电板连接和断开的上下互连布线。当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

96. 发明申请

US20060105576A1 HIGH ION ENERGY AND REATIVE SPECIES PARTIAL PRESSURE PLASMA ASH PROCESS 有权
标题翻译：高离子能量和重要物质部分压力等离子体ASH过程
公开(公告)号：US20060105576A1
公开(公告)日：2006-05-18
申请号：US10904608
申请日：2004-11-18
申请人： Nicholas Fuller , Timothy Dalton
发明人： Nicholas Fuller , Timothy Dalton
IPC分类号： H01L21/00 , H01L21/84 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76802 , G03F7/427 , H01L21/31138
摘要： A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.
摘要翻译：用于经过层级镶嵌处理之后灰化场致光材料的高离子能量和高压O 2 2 / CO基等离子体。优化的等离子体灰化过程在大于约300mT的压力下进行，离子能量大于约500W条件，氧分压大于约85％。高压/高离子能量过程的快速灰分速率和最小解离条件（不施加“源”功率）允许层间电介质和灰分化学之间的最小相互作用，以实现小于约5nm的最小总体侧壁修饰。

97. 发明申请

US20050258542A1 Use of a porous dielectric material as an etch stop layer for non-porous dielectric films 有权
标题翻译：使用多孔电介质材料作为非多孔介电膜的蚀刻停止层
公开(公告)号：US20050258542A1
公开(公告)日：2005-11-24
申请号：US10845718
申请日：2004-05-14
申请人： Nicholas Fuller , Timothy Dalton
发明人： Nicholas Fuller , Timothy Dalton
IPC分类号： H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76808 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed and also because of the relatively uniform line heights made feasible by these unique and seemingly counterintuitive features. The present invention also provides a fluorocarbon-based dual damascene etch process that achieves selective etching of a dense low-k OSG films relative to that of a porous low-k OSG film owing to the tunability of the gas-phase fluorine:carbon ratio (gas dissociation) and ion current below a critical threshold and given the larger carbon content of the porous film relative to that of the dense film.
摘要翻译：具有使用多孔低k OSG膜作为蚀刻停止层的无孔（致密）低k有机硅酸盐玻璃（OSG）膜的互连结构或使用无孔OSG膜作为硬掩模的多孔低k OSG膜用于半导体器件中。新颖的互连结构能够提供改进的器件性能，功能和可靠性，这是由于与传统采用的叠层相比，堆叠的有效介电常数降低，并且还因为这些独特且看似违反直觉的特征使得线的高度相对均匀。本发明还提供了一种基于碳氟化合物的双镶嵌蚀刻工艺，由于气相氟：碳比的可调性，实现了相对于多孔低k OSG膜的致密低k OSG膜的选择性蚀刻（气体离解）和离子电流低于临界阈值，并且给出多孔膜相对于致密膜的碳含量较大。

98. 发明申请

US20050218504A1 FILLED CAVITIES SEMICONDUCTOR DEVICES 审中-公开
标题翻译：填充CAVITIES半导体器件
公开(公告)号：US20050218504A1
公开(公告)日：2005-10-06
申请号：US10708883
申请日：2004-03-30
申请人： Timothy Dalton , John Fitzsimmons , Anthony Stamper
发明人： Timothy Dalton , John Fitzsimmons , Anthony Stamper
IPC分类号： H01L21/311 , H01L21/316 , H01L21/768 , H01L23/14 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/31695 , H01L23/5222 , H01L23/5329 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： In an embodiment of the invention, a dielectric material comprises a matrix of a material selected from the group consisting essentially of organic materials, inorganic materials and organo-silicate materials; a plurality of pores dispersed throughout the matrix; and a gas filling the pores. The gas is selected from the group consisting essentially of inert gases, depositing gases, and breakdown suppressing gases. The filled pore dielectric material is suitably used in a damascene wiring layer. In further embodiments, a plasma device comprises an integrated circuit (IC) chip substrate; at least one dielectric layer having a thickness on a surface of the substrate, a cavity formed in the dielectric layer, at least two electrodes disposed in the cavity; and a plasma gas filling the cavity. The plasma device can operate as a light source or as a switch.
摘要翻译：在本发明的一个实施方案中，电介质材料包括选自基本上由有机材料，无机材料和有机硅酸盐材料组成的组的基体; 分散在整个基质中的多个孔; 和填充孔的气体。气体选自基本上由惰性气体，沉积气体和击穿抑制气体组成的组。填充孔介电材料适用于镶嵌布线层。在另外的实施例中，等离子体器件包括集成电路（IC）芯片衬底; 至少一个介电层，其具有在所述基板的表面上的厚度，在所述介电层中形成的空腔，设置在所述空腔中的至少两个电极; 以及填充空腔的等离子体气体。等离子体装置可以作为光源或开关操作。

99. 发明申请

US20050208742A1 OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING 审中-公开
标题翻译：氧化氮化钛作为双重加工过程中改进的硬质合金
公开(公告)号：US20050208742A1
公开(公告)日：2005-09-22
申请号：US10708648
申请日：2004-03-17
申请人： William America , Larry Clevenger , Andy Cowley , Timothy Dalton , Mark Hoinkis , Kaushik Kumar , Douglas La Tulipe
发明人： William America , Larry Clevenger , Andy Cowley , Timothy Dalton , Mark Hoinkis , Kaushik Kumar , Douglas La Tulipe
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3205 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76811 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76834
摘要： A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.
摘要翻译：描述了用于双镶嵌加工的氧化氮化钽（TaO x N N N x S）硬掩模层的制造方法。精细的双镶嵌加工对硬掩模产生了竞争，冲突的要求。尽管临界尺寸控制需要较厚的硬掩模，但由于厚氮化钽（TaN）的不透明度，光学平版印刷对挫败感到沮丧。该技术通过氧化TaN层来解决厚度增加的TaN硬掩模不透明度问题。 TaN硬掩模的氧化将硬掩模的厚度增加到其原始厚度的两到四倍，同时将其透明度提高了十倍以上。这允许与更厚的硬掩模相关联的更好的CD控制，同时促进光学光刻对准。

100. 发明申请

US20050158985A1 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US20050158985A1
公开(公告)日：2005-07-21
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/4763 , H01L21/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

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