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1. 发明申请

US20050112864A1 Back End Interconnect With a Shaped Interface 有权
标题翻译：后端与异形接口互连
公开(公告)号：US20050112864A1
公开(公告)日：2005-05-26
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe, Jr. , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe, Jr. , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

2. 发明申请

US20060292852A1 BACK END INTERCONNECT WITH A SHAPED INTERFACE 失效
标题翻译：后端互连与形状接口
公开(公告)号：US20060292852A1
公开(公告)日：2006-12-28
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

3. 发明申请

US20060113278A1 Bilayered metal hardmasks for use in dual damascene etch schemes 有权
标题翻译：用于双镶嵌蚀刻方案的双层金属硬掩模
公开(公告)号：US20060113278A1
公开(公告)日：2006-06-01
申请号：US11330834
申请日：2006-01-12
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew Simon , Mark Hoinkis , Steffen Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew Simon , Mark Hoinkis , Steffen Kaldor , Chih-Chao Yang
IPC分类号： B44C1/22 , H01B13/00
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译：用于制造半导体器件的双镶嵌工艺的金属硬掩模。金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

4. 发明申请

US20050112862A1 Crystallographic Modification of Hard mask Properties 失效
标题翻译：硬掩模性能的晶体学修改
公开(公告)号：US20050112862A1
公开(公告)日：2005-05-26
申请号：US10707119
申请日：2003-11-21
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Kaushik Kumar , Stephen Rossnagel , Andrew Simon , Douglas La Tulipe
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Kaushik Kumar , Stephen Rossnagel , Andrew Simon , Douglas La Tulipe
IPC分类号： G03F9/00 , H01L21/033 , H01L21/285 , H01L21/4763 , H01L21/768 , H01L23/544
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/0332 , H01L21/0337 , H01L21/2855 , H01L21/76841 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.
摘要翻译：集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ·cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和通过硬掩模和ILD的中间层降低对准标记。形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

5. 发明申请

US20050158985A1 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US20050158985A1
公开(公告)日：2005-07-21
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/4763 , H01L21/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

6. 发明授权

US06784105B1 Simultaneous native oxide removal and metal neutral deposition method 有权
标题翻译：同时自然氧化物去除和金属中性沉积法
公开(公告)号：US06784105B1
公开(公告)日：2004-08-31
申请号：US10410496
申请日：2003-04-09
申请人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
发明人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
摘要翻译：提供一种制造具有电介质结构的半导体器件的方法，其中使用光刻和蚀刻技术在单个淀积室内使互连结构任意地图案化。在溅射蚀刻工艺之前，电介质结构可任选地被扩散阻挡材料覆盖。该溅射蚀刻工艺用于去除下面的金属导体表面上的自然氧化物，并且包括具有同时沉积金属中性的定向气体轰击。扩散阻挡材料也可以沉积到图案中。

7. 发明授权

US06380628B2 Microstructure liner having improved adhesion 失效
标题翻译：显微组织衬垫具有改进的粘合性
公开(公告)号：US06380628B2
公开(公告)日：2002-04-30
申请号：US09377329
申请日：1999-08-18
申请人： John A. Miller , Andrew Simon , Jill Slattery , Cyprian E. Uzoh , Yun-Yu Wang
发明人： John A. Miller , Andrew Simon , Jill Slattery , Cyprian E. Uzoh , Yun-Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/76862 , H01L21/76816 , H01L21/76843 , H01L21/76865 , H01L21/76871
摘要： A damascene structure, such as a conductive line or via, having a liner with a roughened surface between the substrate and the conductive fill and, preferably, a smooth bottom. The substrate underneath the liner may also have a roughened sidewall and smooth bottom. Such a structure provides enhanced adhesion between one or more layers of the damascene structure. The damascene structure may be manufactured by applying a photoresist over a substrate top surface, exposing the photoresist under conditions that create a standing wave in the resist, and developing the photoresist to provide a pattern having the desired roughened or serrated outline. The pattern is transferred into the substrate, the liner is applied over the substrate bottom and sidewalls, and the liner is filled with conductive material. A roughened liner surface may be achieved by applying a partial layer of liner material over the substrate, removing a portion of the partial layer, and repeating the application and removal steps.
摘要翻译：具有在衬底和导电填料之间具有粗糙表面的衬垫，以及优选光滑底部的镶嵌结构，例如导电线或通孔。衬垫下面的衬底也可以具有粗糙的侧壁和光滑的底部。这种结构提供了镶嵌结构的一层或多层之间增强的附着力。镶嵌结构可以通过在衬底顶表面上施加光致抗蚀剂来制造，在在抗蚀剂中产生驻波的条件下曝光光致抗蚀剂，以及显影光致抗蚀剂以提供具有期望的粗糙化或锯齿形轮廓的图案。将图案转移到衬底中，将衬垫施加在衬底底部和侧壁上，并且衬垫填充有导电材料。可以通过在衬底上施加部分衬里材料层，去除部分层的一部分并重复施加和去除步骤来实现粗糙化衬里表面。

8. 发明申请

US20050167838A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20050167838A1
公开(公告)日：2005-08-04
申请号：US10707996
申请日：2004-01-30
申请人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
发明人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线车道和通道上或附近形成间隙

9. 发明申请

US20120153359A1 NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION 有权
标题翻译：具有差异PT组成的镍 - 硅化物形成
公开(公告)号：US20120153359A1
公开(公告)日：2012-06-21
申请号：US13408246
申请日：2012-02-29
申请人： Asa Frye , Andrew Simon
发明人： Asa Frye , Andrew Simon
IPC分类号： H01L29/772
CPC分类号： H01L21/28518 , H01L29/665
摘要： Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
摘要翻译：本发明的实施例提供一种形成硅化镍的方法。该方法可以包括通过物理气相沉积（PVD）工艺在场效应晶体管（FET）的栅极，源极和漏极区域中的至少一个上沉积第一和第二金属层，其中第一金属层使用含有铂（Pt）的第一镍靶材料沉积，并且使用不比第一镍靶材料中不含铂的第二镍靶材料将第二金属层沉积在第一金属层的顶部上; 以及退火覆盖所述FET的所述第一和第二金属层，以在所述栅极，源极和漏极区域的顶表面处形成含铂的硅化镍层。

10. 发明申请

US20110169058A1 NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION 有权
标题翻译：具有差异PT组成的镍 - 硅化物形成
公开(公告)号：US20110169058A1
公开(公告)日：2011-07-14
申请号：US12684144
申请日：2010-01-08
申请人： Asa Frye , Andrew Simon
发明人： Asa Frye , Andrew Simon
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28518 , H01L29/665
摘要： Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
摘要翻译：本发明的实施例提供一种形成硅化镍的方法。该方法可以包括通过物理气相沉积（PVD）工艺在场效应晶体管（FET）的栅极，源极和漏极区域中的至少一个上沉积第一和第二金属层，其中第一金属层使用含有铂（Pt）的第一镍靶材料沉积，并且使用不比第一镍靶材料中不含铂的第二镍靶材料将第二金属层沉积在第一金属层的顶部上; 以及退火覆盖所述FET的所述第一和第二金属层，以在所述栅极，源极和漏极区域的顶表面处形成含铂的硅化镍层。

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