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91. 发明授权

US09513915B2 Instruction merging optimization 有权
标题翻译：指令合并优化
公开(公告)号：US09513915B2
公开(公告)日：2016-12-06
申请号：US13432537
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： A computer system for optimizing instructions includes a processor including an instruction execution unit configured to execute instructions and an instruction optimization unit configured to optimize instructions and memory to store machine instructions to be executed by the instruction execution unit. The computer system is configured to perform a method including analyzing machine instructions from among a stream of instructions to be executed by the instruction execution unit, the machine instructions including a memory load instruction and a data processing instruction to perform a data processing function based on the memory load instruction, identifying the machine instructions as being eligible for optimization, merging the machine instructions into a single optimized internal instruction, and executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction.
摘要翻译：用于优化指令的计算机系统包括：处理器，包括被配置为执行指令的指令执行单元和被配置为优化指令和存储器以存储由指令执行单元执行的机器指令的指令优化单元。计算机系统被配置为执行一种方法，包括从由指令执行单元执行的指令流中分析机器指令，包括存储器加载指令的机器指令和数据处理指令，以执行基于存储器加载指令，将机器指令识别为符合优化的要求，将机器指令合并到单个优化的内部指令中，以及执行单个优化内部指令以执行对应于存储器加载指令的存储器加载功能和数据处理功能，以及数据处理指令。

92. 发明授权

US09323530B2 Caching optimized internal instructions in loop buffer 有权
公开(公告)号：US09323530B2
公开(公告)日：2016-04-26
申请号：US13432512
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/381 , G06F9/384
摘要： Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.

93. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

94. 发明授权

US08984042B2 Mixed precision estimate instruction computing narrow precision result for wide precision inputs 有权
公开(公告)号：US08984042B2
公开(公告)日：2015-03-17
申请号：US13369470
申请日：2012-02-09
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/38 , G06F7/00 , G06F15/00 , G06F7/483 , G06F7/499
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49905
摘要： A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.

95. 发明授权

US08781865B2 Handling consolidated tickets 失效
标题翻译：处理综合票
公开(公告)号：US08781865B2
公开(公告)日：2014-07-15
申请号：US13570977
申请日：2012-08-09
申请人： John A. Bivens , Valentina Salapura
发明人： John A. Bivens , Valentina Salapura
IPC分类号： G06Q10/00
CPC分类号： G06Q10/06
摘要： Handling problem tickets in a computing environment, in one aspect, may comprise identifying a plurality of tickets generated in the computing environment that are candidates for consolidation. The identifying may be done based on whether the tickets have the same or similar root cause, whether they are generated from virtual machines having same configuration, and/or one or more other criteria. The tickets which are candidates for consolidation may be grouped into a bundled group, and marked as bundled. Resolving a ticket from the bundled group may potentially resolves all tickets from the bundled group.
摘要翻译：在一个方面，在计算环境中处理问题票可以包括识别在计算环境中生成的作为合并的候选者的多个票据。可以基于票据是否具有相同或相似的根本原因来完成识别，无论它们是从具有相同配置的虚拟机生成的，和/或一个或多个其他标准。作为合并候选人的票可以分组为捆绑组，并标记为捆绑。从捆绑组中解决故障单可能会解决捆绑组中的所有故障单。

96. 发明授权

US08756350B2 Method and apparatus for efficiently tracking queue entries relative to a timestamp 失效
标题翻译：相对于时间戳有效跟踪队列条目的方法和装置
公开(公告)号：US08756350B2
公开(公告)日：2014-06-17
申请号：US11768800
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F12/0835 , G06F12/0831
摘要： An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.
摘要翻译：一种用于跟踪在多处理器系统中发送的相干事件信号的装置和方法。该装置包括相干逻辑单元，每个单元具有多个队列结构，每个队列结构与在系统中传输的事件信号的相应发送者相关联。与队列结构相关联的定时电路控制接收的相干事件信号的排队和出队，并且计数器跟踪队列结构中剩余入队的多个相干事件信号，并且从接收到时间戳信号起出队。计数器机构产生一个输出信号，指示在接收时间戳信号时存在于队列结构中的所有相干事件信号已经出队。在一个实施例中，时间戳信号在存储器同步操作的开始被断言，并且输出信号指示当时间戳信号被断言时存在的所有相干事件已经完成。然后可以将该信号用作存储器同步操作的完成条件的一部分。

97. 发明申请

US20140039958A1 HANDLING CONSOLIDATED TICKETS 失效
公开(公告)号：US20140039958A1
公开(公告)日：2014-02-06
申请号：US13570977
申请日：2012-08-09
申请人： John A. Bivens , Valentina Salapura
发明人： John A. Bivens , Valentina Salapura
IPC分类号： G06Q10/06
CPC分类号： G06Q10/06
摘要： Handling problem tickets in a computing environment, in one aspect, may comprise identifying a plurality of tickets generated in the computing environment that are candidates for consolidation. The identifying may be done based on whether the tickets have the same or similar root cause, whether they are generated from virtual machines having same configuration, and/or one or more other criteria. The tickets which are candidates for consolidation may be grouped into a bundled group, and marked as bundled. Resolving a ticket from the bundled group may potentially resolves all tickets from the bundled group.

98. 发明授权

US08621167B2 Using DMA for copying performance counter data to memory 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US08621167B2
公开(公告)日：2013-12-31
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

99. 发明申请

US20130326180A1 MECHANISM FOR OPTIMIZED INTRA-DIE INTER-NODELET MESSAGING COMMUNICATION 有权
标题翻译：优化内部信号通信通信机制
公开(公告)号：US20130326180A1
公开(公告)日：2013-12-05
申请号：US13485074
申请日：2012-05-31
申请人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
发明人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/14
CPC分类号： G06F9/544 , G06F15/167
摘要： Point-to-point intra-nodelet messaging support for nodelets on a single chip that obey MPI semantics may be provided. In one aspect, a local buffering mechanism is employed that obeys standard communication protocols for the network communications between the nodelets integrated in a single chip. Sending messages from one nodelet to another nodelet on the same chip may be performed not via the network, but by exchanging messages in the point-to-point messaging buckets between the nodelets. The messaging buckets need not be part of the memory system of the nodelets. Specialized hardware controllers may be used for moving data between the nodelets and each messaging bucket, and ensuring correct operation of the network protocol.
摘要翻译：可以提供在遵循MPI语义的单个芯片上的节点的点对点节点内消息支持。在一个方面，采用本地缓冲机制，其遵循集成在单个芯片中的节点之间的网络通信的标准通信协议。从同一芯片上的一个节点发送消息到另一个节点可能不是通过网络执行的，而是通过在节点之间的点对点消息存储区中交换消息。消息传递桶不需要是节点的内存系统的一部分。专用硬件控制器可用于在节点和每个消息传送桶之间移动数据，并确保网络协议的正确操作。

100. 发明授权

US08521990B2 Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders 有权
标题翻译：在环网中嵌入全局屏障和集体，每个节点根据类映射将接收器的输入组合到输出到发送器
公开(公告)号：US08521990B2
公开(公告)日：2013-08-27
申请号：US12723277
申请日：2010-03-12
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
IPC分类号： G06F15/16
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
摘要翻译：本发明的实施例提供了一种用于在被组织为环面网络的并行计算机系统中嵌入全局屏障和全局中断网络的方法，系统和计算机程序产品。计算机系统包括多个节点。在一个实施例中，该方法包括从节点的一组接收器中获取输入，将来自接收器的输入划分为多个类，组合每个类的输入以获得结果，并将所述结果发送到一组的节点的发送者。本发明的实施例提供了一种用于将集体网络嵌入组织为环面网络的并行计算机系统中的方法，系统和计算机程序产品。在一个实施例中，该方法包括向环形网络添加集中逻辑以在树结构中的至少一组节点之间路由消息。

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