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91. 发明申请

US20120056275A1 HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE 有权
标题翻译：高性能低功率散热FET器件及其制造方法
公开(公告)号：US20120056275A1
公开(公告)日：2012-03-08
申请号：US12876480
申请日：2010-09-07
申请人： Jin CAI , Toshiharu FURUKAWA , Robert R. ROBISON
发明人： Jin CAI , Toshiharu FURUKAWA , Robert R. ROBISON
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/7833 , H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636
摘要： A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.
摘要翻译：形成半导体器件的方法包括：在衬底中形成场效应晶体管（FET）的沟道; 在衬底中形成重掺杂区域; 以及形成与沟道和重掺杂区相邻的凹槽。该方法还包括：在通道和重掺杂区域的暴露部分上的凹槽中形成未掺杂或轻掺杂的中间层; 以及在中间层上形成源极和漏极区域，使得源极和漏极区域通过中间层与重掺杂区域间隔开。

92. 发明申请

US20110266621A1 FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管
公开(公告)号：US20110266621A1
公开(公告)日：2011-11-03
申请号：US13179635
申请日：2011-07-11
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

93. 发明授权

US08043966B2 Method for monitoring patterning integrity of etched openings and forming conductive structures with the openings 有权
标题翻译：用于监测蚀刻开口的图案完整性并与开口形成导电结构的方法
公开(公告)号：US08043966B2
公开(公告)日：2011-10-25
申请号：US12101329
申请日：2008-04-11
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , C25D5/10 , C25D5/12 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76802 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.
摘要翻译：公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等）。）在这样的开口内。该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。

94. 发明申请

US20110204384A1 METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR 有权
标题翻译：在SOI绝缘体（SOI）波形上形成具有嵌入式和表面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和平面场效应晶体管的设计结构
公开(公告)号：US20110204384A1
公开(公告)日：2011-08-25
申请号：US13101267
申请日：2011-05-05
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L27/12 , H01L29/12 , G06F17/50 , B82Y99/00
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

95. 发明授权

US07985643B2 Semiconductor transistors with contact holes close to gates 有权
标题翻译：具有靠近门的接触孔的半导体晶体管
公开(公告)号：US07985643B2
公开(公告)日：2011-07-26
申请号：US12052855
申请日：2008-03-21
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David Vaclav Horak , Charles William Koburger, III , William Robert Tonti
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David Vaclav Horak , Charles William Koburger, III , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114
摘要： A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.
摘要翻译：半导体结构。该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

96. 发明申请

US20110169129A1 ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
标题翻译：抗保护器件结构和电镀电路结构与方法
公开(公告)号：US20110169129A1
公开(公告)日：2011-07-14
申请号：US13072023
申请日：2011-03-25
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

97. 发明授权

US07935621B2 Anti-fuse device structure and electroplating circuit structure and method 有权
标题翻译：反熔丝器件结构及电镀电路结构及方法
公开(公告)号：US07935621B2
公开(公告)日：2011-05-03
申请号：US12031761
申请日：2008-02-15
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

98. 发明申请

US20110095366A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 有权
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20110095366A1
公开(公告)日：2011-04-28
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/786 , H01L21/762 , H01L29/02
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

99. 发明申请

US20110027951A1 SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT 有权
标题翻译：常规平面设备和水平CNT的共享门
公开(公告)号：US20110027951A1
公开(公告)日：2011-02-03
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

100. 发明申请

US20100330756A1 INTEGRATED CIRCUIT STRUCTURE MANUFACTURING METHODS USING HARD MASK AND PHOTORESIST COMBINATION 审中-公开
标题翻译：使用硬掩模和光电组合的集成电路结构制造方法
公开(公告)号：US20100330756A1
公开(公告)日：2010-12-30
申请号：US12491270
申请日：2009-06-25
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of manufacturing an integrated circuit structure implants a first-type of channel implant in a first area of a substrate and implants a second-type of channel implant in a second area of the substrate. The method forms at least one first gate conductor above the first area of the substrate and forms at least one second gate conductor above the second area of the substrate. The method forms a hard mask over the first gate conductor, the second gate conductor, and the substrate. The hard mask comprises an oxide or a nitride and patterns an organic photoresist over the hard mask, to leave the organic photoresist on areas of the hard mask that are above the first area of the substrate. The method removes portions of the hard mask not protected by the organic photoresist to leave the hard mask on the first area of the substrate and not on the second area of the substrate. The method then removes the organic photoresist, implants impurities in the second area of the substrate to form source and drain regions adjacent the second gate conductor; and removes the hard mask using a wet etching process.
摘要翻译：一种制造集成电路结构的方法是将衬底的第一区域中的第一种沟道注入植入，并在衬底的第二区域中注入第二类沟道注入。该方法在衬底的第一区域之上形成至少一个第一栅极导体，并在衬底的第二区域上方形成至少一个第二栅极导体。该方法在第一栅极导体，第二栅极导体和衬底上形成硬掩模。硬掩模包括氧化物或氮化物，并且在硬掩模上形成有机光致抗蚀剂，以将有机光致抗蚀剂留在位于衬底的第一区域上方的硬掩模的区域上。该方法除去未被有机光致抗蚀剂保护的硬掩模的部分，以将硬掩模留在衬底的第一区域上，而不在衬底的第二区域上。该方法然后去除有机光致抗蚀剂，在衬底的第二区域内植入杂质以形成邻近第二栅极导体的源区和漏区; 并使用湿蚀刻工艺去除硬掩模。

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