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91. 发明授权

US07238607B2 Method to minimize formation of recess at surface planarized by chemical mechanical planarization 有权
标题翻译：通过化学机械平面化平坦化的表面减少凹陷形成的方法
公开(公告)号：US07238607B2
公开(公告)日：2007-07-03
申请号：US11237169
申请日：2005-09-28
申请人： Samuel V. Dunton , S. Brad Herner
发明人： Samuel V. Dunton , S. Brad Herner
IPC分类号： H01L21/4763
CPC分类号： G11C11/39 , G11C5/02 , G11C17/16 , G11C2213/71 , G11C2213/77
摘要： When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.
摘要翻译：当化学机械平面化（CMP）用于平坦化表面共同图案化特征和电介质填充时，其中图案特征和填充物由具有非常不同的CMP去除速率或特性的材料形成，平坦化表面可能具有过度粗糙，凹陷或凹陷可能发生，或者一个或多个，或者材料可能被损坏。在平面度重要的结构中，通过在图案化特征上形成覆盖层可以防止这些问题，其中形成覆盖层的材料的CMP去除速率类似于介电填料的CMP去除速率。

92. 发明授权

US06956278B2 Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers 有权
标题翻译：低密度，高电阻率氮化钛层，用作低漏电介质层的接触
公开(公告)号：US06956278B2
公开(公告)日：2005-10-18
申请号：US10611245
申请日：2003-06-30
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/02 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L23/525 , H01L29/49 , H01L29/78 , H01L29/00 , H01L29/04
CPC分类号： H01L23/5252 , H01L21/28088 , H01L21/28273 , H01L21/28282 , H01L21/2855 , H01L21/3205 , H01L28/60 , H01L29/4966 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.
摘要翻译：当与电介质耦合时，PVD溅射沉积材料（优选氮化钛）的低密度，高电阻率层产生用于半导体器件的优异的低漏电绝缘屏障。该材料是通过溅射方法产生的，这些方法使离子以较低的能量冲击沉积表面，例如在离子金属等离子体室中，没有自偏压加速垂直于沉积表面的离子，或者在具有压力增加的标准PVD室中。

93. 发明授权

US06815077B1 Low temperature, low-resistivity heavily doped p-type polysilicon deposition 有权
标题翻译：低温，低电阻率重掺杂p型多晶硅沉积
公开(公告)号：US06815077B1
公开(公告)日：2004-11-09
申请号：US10441601
申请日：2003-05-20
申请人： S. Brad Herner , Mark H. Clark
发明人： S. Brad Herner , Mark H. Clark
IPC分类号： B32B1504
CPC分类号： H01L21/8221 , C23C16/045 , C23C16/24 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/28525 , H01L27/1052
摘要： A method to create a low resistivity P+ in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.
摘要翻译：在低温下从SiH4和BCl3生成低电阻P +原位掺杂多晶硅膜的方法，无需退火。在使用这些源气体的常规掺杂剂浓度下，随着沉积温度降低到约550℃以下，沉积速率降低并且薄层电阻增加，使得生产高质量膜不可能。然而，通过流动非常大量的BCl 3，使得所得膜中硼原子的浓度为约7×10 20或更高，沉积速率和薄层电阻提高，并且产生高质量的膜。

94. 发明授权

US08450835B2 Reverse leakage reduction and vertical height shrinking of diode with halo doping 有权
公开(公告)号：US08450835B2
公开(公告)日：2013-05-28
申请号：US12149217
申请日：2008-04-29
申请人： Xiying Chen , Mark H. Clark , S. Brad Herner , Tanmay Kumar
发明人： Xiying Chen , Mark H. Clark , S. Brad Herner , Tanmay Kumar
IPC分类号： H01L29/06
CPC分类号： H01L29/868 , H01L29/1606 , H01L29/8615
摘要： One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

95. 发明授权

US08362356B2 Intermetal stack for use in a photovoltaic device 失效
标题翻译：用于光伏器件的金属间叠层
公开(公告)号：US08362356B2
公开(公告)日：2013-01-29
申请号：US12540463
申请日：2009-08-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/1896 , H01L31/022425 , H01L31/03921 , H01L31/072 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a titanium layer in contact with the lamina, which reacts to form titanium silicide, a non-reactive barrier layer to check the silicide reaction, a low-resistance layer, and an adhesion layer to help adhesion to the receiver element.
摘要翻译：供体硅晶片可以结合到基底和从施主晶片分离的薄片。可以从结合到衬底的薄片形成光伏电池。描述了优化用于这种电池的金属间堆叠。金属间堆叠可以包括与层接触的钛层，其与反应形成硅化钛，用于检查硅化物反应的非反应性阻挡层，低电阻层和粘合层以帮助粘附到接收器元件。

96. 发明授权

US08247260B2 Method to form a photovoltaic cell comprising a thin lamina 有权
标题翻译：形成包括薄层的光伏电池的方法
公开(公告)号：US08247260B2
公开(公告)日：2012-08-21
申请号：US12499294
申请日：2009-07-08
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/00 , H01L21/30 , H01L31/042
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.
摘要翻译：通过在诸如半导体晶片的施主体的表面下方注入气体离子形成非常薄的光伏电池。离子注入限定了解理面，随后的步骤在切割平面处从晶片剥离薄层。光伏电池，或光伏电池的基极或发射极的全部或一部分形成在层内。在优选实施例中，在切割步骤之前将晶片固定到接收器。电接触可以形成在层的两个表面上，或仅形成在一个表面上。

97. 发明授权

US08203864B2 Memory cell and methods of forming a memory cell comprising a carbon nanotube fabric element and a steering element 有权
标题翻译：存储单元和形成包含碳纳米管织物元件和转向元件的存储单元的方法
公开(公告)号：US08203864B2
公开(公告)日：2012-06-19
申请号：US13083746
申请日：2011-04-11
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L51/0048 , H01L51/0595 , Y10S977/742
摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.
摘要翻译：提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。还提供其他方面。

98. 发明申请

US20120012808A1 DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING 有权
标题翻译：沉积半导体结构以最小化N型掺杂物扩散和制备方法
公开(公告)号：US20120012808A1
公开(公告)日：2012-01-19
申请号：US13247723
申请日：2011-09-28
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L47/00
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.
摘要翻译：提供了存储单元，其包括半导体柱和耦合到半导体柱的可逆状态变换元件。半导体柱包括第一导电类型的重掺杂底部区域，第二导电类型的重掺杂顶部区域，以及插入并接触顶部区域和底部区域之间的轻掺杂或本征中间区域。中间区域包括第一比例的锗，并且顶部区域或底部区域不包含锗，或者包括小于第一比例的第二比例的锗。可逆态变化元件包括选自NiO，Nb 2 O 5，TiO 2，HfO 2，Al 2 O 3，CoO，MgO x，CrO 2，VO，BN和AlN的电阻率切换金属氧化物或氮化物层。提供了许多其他方面。

99. 发明授权

US08072791B2 Method of making nonvolatile memory device containing carbon or nitrogen doped diode 有权
标题翻译：制造含碳或氮掺杂二极管的非易失性存储器件的方法
公开(公告)号：US08072791B2
公开(公告)日：2011-12-06
申请号：US11819041
申请日：2007-06-25
申请人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
发明人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C11/36 , H01L27/101 , H01L27/1021
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.
摘要翻译：制造非易失性存储器件的方法包括：形成第一电极，形成至少一个包括硅，锗或硅 - 锗二极管的非易失性存储单元，用氮或碳中的至少一种掺杂二极管，并形成第二电极所述至少一个非易失性存储单元。

100. 发明申请

US20110266514A1 MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT 有权
标题翻译：包含碳纳米管织物元件和转向元件的存储单元
公开(公告)号：US20110266514A1
公开(公告)日：2011-11-03
申请号：US13182960
申请日：2011-07-14
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L45/00 , B82Y99/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
摘要翻译：提供了一种存储单元，所述存储单元包括具有垂直取向的p-i-n结的转向元件和碳纳米管织物。导向元件和碳纳米管织物电串联布置，整个存储单元形成在基板上。还提供其他方面。

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