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91. 发明授权

US06424199B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06424199B1
公开(公告)日：2002-07-23
申请号：US09978022
申请日：2001-10-17
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03K3013
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

92. 发明授权

US06377101B1 Variable delay circuit and semiconductor integrated circuit device 有权
标题翻译：可变延迟电路和半导体集成电路器件
公开(公告)号：US06377101B1
公开(公告)日：2002-04-23
申请号：US09510299
申请日：2000-02-22
申请人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
发明人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/131 , H03K5/133 , H03L7/07 , H03L7/0814 , H03L7/0818 , H03L7/087 , H04L7/033
摘要： A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
摘要翻译：可变延迟电路包括具有第一延迟量的第一栅极和具有大于第一延迟量的第二延迟量的第二栅极。第一延迟量和第二延迟时间之间的差小于第一延迟量。

93. 发明授权

US06292426B1 Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
标题翻译：在单个芯片上具有SRAM和DRAM的半导体存储器件
公开(公告)号：US06292426B1
公开(公告)日：2001-09-18
申请号：US09531498
申请日：2000-03-21
申请人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
发明人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
IPC分类号： G11C800
CPC分类号： G11C11/005
摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
摘要翻译：半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。在芯片上提供DRAM，DRAM包括DRAM单元阵列。地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

94. 发明授权

US06205082B1 LSI device with memory and logics mounted thereon 有权
标题翻译：具有安装在其上的存储器和逻辑的LSI器件
公开(公告)号：US06205082B1
公开(公告)日：2001-03-20
申请号：US09304589
申请日：1999-05-04
申请人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
发明人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C800
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C2207/105 , G11C2207/108 , H01L24/45 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/00
摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.
摘要翻译：数据信号从第一芯片的输出电路输出，并经由数据引线，基于第一芯片中的输出时钟发送到第二芯片中的数据输入端子，该输出时钟发送到第二芯片。并且第二芯片中的输入电路响应于从第一芯片中的输出时钟产生的传输时钟，接收数据信号并将其传送到内部。因此，与第一芯片中的单个参考时钟同步，数据信号可以从第一芯片高速传输到第二芯片。

95. 发明授权

US6037813A Semiconductor device capable of selecting operation mode based on clock frequency 失效
标题翻译：能够基于时钟频率选择操作模式的半导体装置
公开(公告)号：US6037813A
公开(公告)日：2000-03-14
申请号：US880912
申请日：1997-06-23
申请人： Satoshi Eto , Masao Taguchi
发明人： Satoshi Eto , Masao Taguchi
IPC分类号： H01L27/04 , G06F1/12 , G06F12/00 , G06F12/06 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/82 , H01L21/822 , H03K5/26 , H03K19/00 , H03L7/08 , H03L7/081 , G06F1/04
CPC分类号： H03L7/0805 , G06F1/12 , H03K19/0016 , H03K5/26 , H03L7/08 , H03L7/0814
摘要： A semiconductor device which operates in synchronism with a first clock externally provided. The semiconductor device includes a clock-generation circuit generating a second clock which maintains a predetermined phase relation with the first clock, a check circuit for checking a frequency of the first clock based on at least one internal signal generated by the clock-generation circuit, and an internal circuit which switches an operation mode according to results of the checking.
摘要翻译：与外部提供的第一时钟同步工作的半导体器件。半导体器件包括产生与第一时钟保持预定相位关系的第二时钟的时钟产生电路，用于基于由时钟发生电路产生的至少一个内部信号来检查第一时钟的频率的校验电路，以及根据检查结果切换操作模式的内部电路。

96. 发明授权

US6026041A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6026041A
公开(公告)日：2000-02-15
申请号：US22403
申请日：1998-02-12
申请人： Takaaki Suzuki , Hiroyuki Kobayashi , Toyomitsu Matsumoto , Masao Taguchi , Yoshihiro Takemae
发明人： Takaaki Suzuki , Hiroyuki Kobayashi , Toyomitsu Matsumoto , Masao Taguchi , Yoshihiro Takemae
IPC分类号： G11C11/409 , G11C7/12 , G11C7/22 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C7/22 , G11C11/406 , G11C7/12
摘要： A semiconductor memory device includes a memory part which stores data, a decoder which decodes a command externally supplied to the semiconductor memory device, and a precharge protection circuit which dynamically determines, based on the command decoded by the decoder, a period necessary to precharge a predetermined circuit part of the semiconductor memory device, so that a precharge operation on the predetermined circuit part can be protected.
摘要翻译：一种半导体存储器件包括存储数据的存储器部分，对外部提供给半导体存储器件的指令进行解码的解码器，以及预充电保护电路，其基于解码器解码的命令动态地确定预充电所需的时间半导体存储器件的预定电路部分，从而可以保护对预定电路部分的预充电操作。

97. 发明授权

US5955889A Electronic circuit apparatus for transmitting signals through a bus and semiconductor device for generating a predetermined stable voltage 失效
公开(公告)号：US5955889A
公开(公告)日：1999-09-21
申请号：US445099
申请日：1995-05-19
申请人： Masao Taguchi , Satoshi Eto , Yoshinori Okajima
发明人： Masao Taguchi , Satoshi Eto , Yoshinori Okajima
IPC分类号： H03K17/16 , H04L25/02
CPC分类号： H04L25/0278 , H03K17/16 , H04L25/028 , H04L25/0292 , H04L25/0298
摘要： An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

98. 发明授权

US5707672A Method for sterilizing and packaging solid foods 失效
标题翻译：消毒和包装固体食品的方法
公开(公告)号：US5707672A
公开(公告)日：1998-01-13
申请号：US519806
申请日：1995-08-24
申请人： Masao Taguchi , Yoshitaka Hirano , Koji Sengoku , Masayuki Nakatani , Mahito Orii , Akifumi Fujita
发明人： Masao Taguchi , Yoshitaka Hirano , Koji Sengoku , Masayuki Nakatani , Mahito Orii , Akifumi Fujita
IPC分类号： A23L1/00 , A23L1/10 , A23L1/16 , A23L1/182 , A23L1/212 , A23L1/31 , A23L1/317 , A23L3/00 , A23L3/005 , A23L3/02 , A23L3/10 , B65B25/00 , A23C3/16
CPC分类号： B65B25/001 , A23L3/02 , A23L3/10 , A23L7/111 , A23L7/1965
摘要： A method for sterilizing and packing a solid food comprises the steps of charging a solid food in a retainer, whose upper portion is opened, in a layer having an approximately uniform thickness, sterilizing the retainer through heating, cooling it with cooling air and/or cooling water, transferring the solid food contained in the retainer to a sterilized packaging container and then aseptically sealing the container. The method permits efficient and rapid heating and cooling of a solid food because of the direct contact between steam or cooling air and/or cooling water and the food without causing a problem such that the packaging container becomes dirty during the sterilization through heating and does not give out any remaining bad smell. Therefore, excess softening and/or destruction of the solid foods as well as any deterioration thereof due to decomposition and alteration of the nutritive substances and flavoring substances present therein can thus be limited to the lowest possible level.
摘要翻译：消毒和包装固体食物的方法包括以下步骤：将固体食物装入上部打开的保持器中，具有大致均匀厚度的层，通过加热对保持器进行灭菌，用冷却空气和/或冷却水，将包含在保持器中的固体食物转移到灭菌的包装容器中，然后无菌密封容器。该方法允许由于蒸汽或冷却空气和/或冷却水与食物之间的直接接触而导致固体食物的有效和快速的加热和冷却，而不会引起问题，使得包装容器在通过加热灭菌期间变脏，并且不会发出任何残留的气味。因此，固体食品的过度软化和/或破坏以及由于其中存在的营养物质和调味物质的分解和改变而导致的任何劣化因此可以被限制在尽可能低的水平。

99. 发明授权

US5631547A Power-supply-voltage reduction device, semiconductor integrated circuit device including the reduction device and method of producing electronic device including such devices 失效
标题翻译：电源电压降低装置，包括所述还原装置的半导体集成电路装置和包括这种装置的电子装置的制造方法
公开(公告)号：US5631547A
公开(公告)日：1997-05-20
申请号：US377588
申请日：1995-01-24
申请人： Shin-ya Fujioka , Masao Taguchi
发明人： Shin-ya Fujioka , Masao Taguchi
IPC分类号： G11C11/407 , H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L21/00
CPC分类号： H01L27/0218
摘要： A power-supply-voltage reduction device including a voltage reduction circuit which has a plurality of transistors and a voltage control circuit. The plurality of transistors have first current electrodes to be supplied with an external power supply voltage, control electrodes receiving a control signal and second current electrodes which are connected together to an output port, the second current electrodes producing a reduced power supply voltage which is generated from the external power supply voltage according to the control signal, at the output port. The voltage control circuit generates the control signal based on a comparison of the reduced power supply voltage and a reference voltage, and controls at least one of the plurality of transistors so as to maintain the reduced power supply voltage substantially to a level of the reference voltage. Since this power-supply-voltage reduction device is constructed with the plurality of transistors for a low external power supply voltage, this device may have a sufficient current supply ability to achieve a stable operating speed and a stable reduced supply voltage.
摘要翻译：一种电源电压降低装置，包括具有多个晶体管的电压降低电路和电压控制电路。多个晶体管具有被提供有外部电源电压的第一电流电极，接收控制信号的控制电极和连接到输出端口的第二电流电极，第二电流电极产生降低的电源电压，该电源电压被产生从外部电源电压根据控制信号，在输出端口。电压控制电路基于降低的电源电压和参考电压的比较来产生控制信号，并且控制多个晶体管中的至少一个，以将降低的电源电压保持在基准电压的水平。由于该电源电压降低装置由多个用于低外部电源电压的晶体管构成，所以该装置可以具有足够的电流供应能力以实现稳定的操作速度和稳定的降低的电源电压。

100. 发明授权

US5607821A Optical exposure method 失效
标题翻译：光学曝光方法
公开(公告)号：US5607821A
公开(公告)日：1997-03-04
申请号：US510128
申请日：1995-08-01
申请人： Tamae Haruki , Kenji Nakagawa , Masao Taguchi , Hiroyuki Tanaka , Satoru Asai , Isamu Hanyu
发明人： Tamae Haruki , Kenji Nakagawa , Masao Taguchi , Hiroyuki Tanaka , Satoru Asai , Isamu Hanyu
IPC分类号： G03F7/20 , G03F7/207 , G03C5/04 , G03B27/32 , G03B27/68 , G03B27/72
CPC分类号： G03F7/70566 , G03F7/201 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70241 , G03F7/70283 , G03F7/70583
摘要： An optical exposure method in photolithography applied for precise processing when semiconductor devices are produced. A pattern on a photomask is projected and exposed on a register on a base plate with an exposure device including a deformation illumination system, a photomask and a projection lens. The deformation illumination system is composed of a light source, a diaphragm and a condenser lens, and the diaphragm is provided with a linear through-hole. The optical exposure method uses a ray of linear light for illumination or two rays of linear light for illumination that are parallel with the pattern. The two rays of linear light are symmetrical with respect to an optical axis. These rays are parallel with the pattern in a position separate from the optical axis of the exposure device when the photomask pattern is a line and space pattern.
摘要翻译：在制造半导体器件时，用于精密加工的光刻中的光学曝光方法。光掩模上的图案被投影并暴露在具有包括变形照明系统，光掩模和投影透镜的曝光装置的基板上的寄存器上。变形照明系统由光源，光阑和聚光透镜组成，隔膜设有直线通孔。光学曝光方法使用用于照明的线性光线或与图案平行的用于照明的两束线性光。两条线性光线相对于光轴对称。当光掩模图案是线和空间图案时，这些光线与图案平行于与曝光装置的光轴分离的位置。

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