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1. 发明授权

US06872620B2 Trench capacitors with reduced polysilicon stress 失效
标题翻译：减少多晶硅应力的沟槽电容器
公开(公告)号：US06872620B2
公开(公告)日：2005-03-29
申请号：US10441887
申请日：2003-05-20
申请人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
摘要翻译：半导体衬底中的深沟槽（DT）电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。在轴环下形成一个外板。电容电介质形成在轴环下面的DT壁上。节点电极形成在DT上，凹陷在DT顶部下方。衣领凹入DT。在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。可以在形成凹陷环的外围边缘之后形成盖，然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质，例如， Ge，进入节点电极和带子。或者，节点电极凹进，随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。

2. 发明授权

US06444516B1 Semi-insulating diffusion barrier for low-resistivity gate conductors 失效
标题翻译：用于低电阻率栅极导体的半绝缘扩散阻挡层
公开(公告)号：US06444516B1
公开(公告)日：2002-09-03
申请号：US09613197
申请日：2000-07-07
申请人： Lawrence Alfred Clevenger , Jack A. Mandelman , Rajarao Jammy , Oleg Gluschenkov , Irene Lennox McStay , Kwong Hon Wong , Johnathan Faltermeier
发明人： Lawrence Alfred Clevenger , Jack A. Mandelman , Rajarao Jammy , Oleg Gluschenkov , Irene Lennox McStay , Kwong Hon Wong , Johnathan Faltermeier
IPC分类号： H01L218234
CPC分类号： H01L21/28044 , H01L29/4941
摘要： A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.
摘要翻译：用于半导体器件的栅极结构，特别是用于诸如CMOS技术的应用的MOSFET。栅结构需要在半导体衬底上形成电绝缘层，形成多晶硅栅电极。栅极结构还包括通过具有半绝缘性质的扩散阻挡层与栅电极电连接的栅极导体。调整扩散阻挡层的组成和厚度，使得阻挡层有效地阻挡栅极导体和多晶硅栅电极之间的扩散和混合，但提供足够的电容耦合和/或电流泄漏，从而不显着增加栅极门结构的传播延迟。

3. 发明授权

US06724088B1 Quantum conductive barrier for contact to shallow diffusion region 有权
标题翻译：用于接触浅扩散区的量子导电屏障
公开(公告)号：US06724088B1
公开(公告)日：2004-04-20
申请号：US09295132
申请日：1999-04-20
申请人： Rajarao Jammy , Jack A. Mandelman
发明人： Rajarao Jammy , Jack A. Mandelman
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L23/485 , H01L29/0895 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Structures such as source/drain contacts of improved reliability are enabled by the creation and use of quantum conductive barrier layers at the interface between the electrical contact and the shallow diffusion source/drain region. The quantum conductive layers are preferably nitrides or oxynitrides. The improved structure is preferably part of a transistor structure of an integrated circuit device. The contacts structures are especially useful for devices employing ultra-shallow junctions.
摘要翻译：通过在电接触和浅扩散源极/漏极区之间的界面处产生和使用量子传导阻挡层，能够实现诸如具有改善的可靠性的源/漏触点的结构。量子导电层优选为氮化物或氮氧化物。改进的结构优选地是集成电路器件的晶体管结构的一部分。触点结构对于采用超浅结的器件特别有用。

4. 发明授权

US06518119B2 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06518119B2
公开(公告)日：2003-02-11
申请号：US09886065
申请日：2001-06-21
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

5. 发明授权

US06236077B1 Trench electrode with intermediate conductive barrier layer 失效
标题翻译：带中间导电阻挡层的沟槽电极
公开(公告)号：US06236077B1
公开(公告)日：2001-05-22
申请号：US09295136
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10861 , H01L29/66181 , H01L29/945
摘要： Reduced scale trench capacitor structures of improved reliability and decreased series resistance are enabled by the creation and use of conductive barrier layers at intermediate points in the trench electrode structure. The conductive barrier layer is preferably either an intrinsically conductive compound barrier or a quantum conductive barrier. The capacitor structures are preferably characterized by a lower electrode region of very high dopant concentration.
摘要翻译：通过在沟槽电极结构的中间点处产生和使用导电阻挡层，可实现提高可靠性和降低串联电阻的缩小沟槽电容器结构。导电阻挡层优选为本征导电化合物屏障或量子导电屏障。电容器结构的特征在于具有非常高掺杂剂浓度的下电极区域。

6. 发明授权

US06194736B1 Quantum conductive recrystallization barrier layers 失效
标题翻译：量子导电重结晶阻挡层
公开(公告)号：US06194736B1
公开(公告)日：2001-02-27
申请号：US09213674
申请日：1998-12-17
申请人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
发明人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
IPC分类号： H01L2906
CPC分类号： H01L29/66181 , H01L21/02667 , H01L21/2022 , H01L27/10867
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用量子传导重结晶阻挡层，能够实现提高可靠性和/或增加组合选择的缩小结构。量子导电层优选用于沟槽电容器中以用作再结晶屏障。

7. 发明授权

US06544874B2 Method for forming junction on insulator (JOI) structure 失效
标题翻译：用于形成绝缘体结（JOI）结构的方法
公开(公告)号：US06544874B2
公开(公告)日：2003-04-08
申请号：US09928759
申请日：2001-08-13
申请人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L213205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译：提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。

8. 发明授权

US06404000B1 Pedestal collar structure for higher charge retention time in trench-type DRAM cells 失效
标题翻译：基座领结构，在沟槽式DRAM单元中具有更高的电荷保留时间
公开(公告)号：US06404000B1
公开(公告)日：2002-06-11
申请号：US09599261
申请日：2000-06-22
申请人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
发明人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.
摘要翻译：一种在衬底中形成有沟槽的存储器结构。环状氧化物位于沟槽的上部，并且包括基座部分。还公开了一种形成具有带衬垫环的环形氧化物的存储器件的方法。

9. 发明授权

US06259129B1 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06259129B1
公开(公告)日：2001-07-10
申请号：US09295133
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

10. 发明授权

US06222218B1 DRAM trench 失效
标题翻译： DRAM沟槽
公开(公告)号：US06222218B1
公开(公告)日：2001-04-24
申请号：US09152835
申请日：1998-09-14
申请人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
摘要翻译：本发明涉及制造半导体存储器结构，特别是深沟槽半导体存储器件的工艺，其中将温度敏感的高介电常数材料并入电容器的存储节点中。具体地，本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。此外，本发明的方法限制了埋层扩散的程度，从而改善阵列MOSFET的电特性。

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