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    • 8. 发明授权
    • System, apparatus and method to improve analog-to-digital converter output
    • 提高模数转换器输出的系统,装置和方法
    • US09054720B2
    • 2015-06-09
    • US13976329
    • 2012-04-19
    • Nicholas P. CowleyIsaac Ali
    • Nicholas P. CowleyIsaac Ali
    • H03M1/06H03M1/08H03M1/10H03M1/00H03M1/12
    • H03M1/08H03M1/00H03M1/0695H03M1/1028H03M1/12H03M1/1215
    • According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample.
    • 根据各种实施例,提出了一种涉及确定和校正模数(AD)转换器阵列(可被实现为宽带ADC的一部分)的输出采样之间的信号不平衡的系统,装置和方法, 。 统计模块和校正模块与A-D转换器阵列相关联。 统计模块被配置为从多个A-D转换器接收数字样本,并且使用从其接收的一组数字样本为每个A-D转换器生成统计采样值。 校正模块被配置为,对于多个AD转换器中的至少一个,通过将多个AD转换器中的至少一个AD转换器的统计采样值与参考值进行比较来确定偏移值,并将偏移值应用于 来自该至少一个AD转换器的数字样本以产生经校正的数字样本。
    • 9. 发明授权
    • Methods and arrangements for high-speed digital-to-analog conversion
    • 高速数模转换的方法和布置
    • US08823568B2
    • 2014-09-02
    • US13631858
    • 2012-09-28
    • Nicholas P. CowleyIsaac Ali
    • Nicholas P. CowleyIsaac Ali
    • H03M1/66
    • H03M1/662
    • Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output.
    • 实施例可以包括诸如用于信号的高速数模转换的硬件和/或代码的逻辑。 许多实施例包括解复用器以将位集合分配给数模转换器,数模转换器用于接收位组并且同时操作以将位组从信号段的数字表示转换为输出模拟 信号段和交织器,以在序列中对来自每个数模转换器的模拟信号段进行交织以产生模拟信号。 在许多实施例中,交织器适于通过将模拟信号段中的每一个的大小锁存到接近于时钟周期端的交错输出来对模拟信号段进行交织,以衰减每个模拟信号段的幅度中的非线性 输出大小。