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1. 发明授权

US5192715A Process for avoiding spin-on-glass cracking in high aspect ratio cavities 失效
标题翻译：避免在高纵横比腔中旋转玻璃裂纹的方法
公开(公告)号：US5192715A
公开(公告)日：1993-03-09
申请号：US873920
申请日：1992-04-24
申请人： John W. Sliwa, Jr. , Pankaj Dixit
发明人： John W. Sliwa, Jr. , Pankaj Dixit
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/522 , H01L23/5329 , H01L2924/0002 , Y10S438/902
摘要： Before spin-on-glass (SOG) is applied and soft-cured over metal traces (10) having a height/width aspect ratio (of the spaces) of at least 1, the aluminum metal traces are selectively coated with selective tungsten (16). After SOG (18) is spun on and soft-cured, it is etched back to expose the metal interconnects. A selective tungsten wet etch in H.sub.2 O.sub.2 detaches the SOG from the metal walls, leaving silt-like voids (20). Stress-free SOG hard curing may now proceed. A capping layer (22) of SOG may now be applied, soft-cured, then hard-cured. Alternatively, other dielectric materials may be applied as the capping layer. Further, interfacial lateral sidewall voids (24) may be deliberately left unfilled, by employing a capping layer (22') of vapor-deposited oxide. The unfilled voids have a dielectric constant of 1.0, which is useful in extremely high speed devices. The resulting structure is comparatively stress-free as fabricated and is resistant to later environmentally-induced brittle tensile fracture.
摘要翻译：在旋涂玻璃（SOG）被施加并软化固化在具有至少1的高度/宽度纵横比（空间）的金属迹线（10）之后，铝金属迹线选择性地涂覆有选择性钨（16 ）。在将SOG（18）纺丝并软化后，将其回蚀以暴露金属互连。 H 2 O 2中的选择性钨湿蚀刻将SOG从金属壁分离出来，留下淤泥状空隙（20）。现在可以进行无压力的SOG硬化。现在可以施加SOG的覆盖层（22），软化，然后硬化。或者，可以施加其它电介质材料作为覆盖层。此外，通过采用蒸镀氧化物的覆盖层（22'），界面侧向侧壁空隙（24）可有意留下未填充。未填充的空隙的介电常数为1.0，这在非常高速的装置中是有用的。所得到的结构在制造时是相对无应力的，并且耐受以后的环境诱导的脆性拉伸断裂。

2. 发明授权

US5119164A Avoiding spin-on-glass cracking in high aspect ratio cavities 失效
标题翻译：避免在高纵横比的空腔中进行旋涂玻璃开裂
公开(公告)号：US5119164A
公开(公告)日：1992-06-02
申请号：US652306
申请日：1991-02-05
申请人： John W. Sliwa, Jr. , Pankaj Dixit
发明人： John W. Sliwa, Jr. , Pankaj Dixit
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/522 , H01L23/5329 , H01L2924/0002
摘要： Before spin-on-glass (SOG) is applied and soft-cured over metal traces (10) having a height/width aspect ratio (of the spaces) of at least 1, the aluminum metal traces are selectively coated with selective tungsten (16). After SOG (18) is spun on and soft-cured, it is etched back to expose the metal interconnects. A selective tungsten wet etch in H.sub.2 O.sub.2 detaches the SOG from the metal walls, leaving silt-like voids (20). Stress-free SOG hard curing may now proceed. A capping layer (22) of SOG may now be applied, soft-cured, then hard-cured. Alternatively, other dielectric materials may be applied as the capping layer. Further, interfacial lateral sidewall voids (24) may be deliberately left unfilled, by employing a capping layer (24') of vapor-deposited oxide. The unfilled voids have a dielectric constant of 1.0, which is useful in extremely high speed devices. The resulting structure is comparatively stress-free as fabricated and is resistant to later environmentally-induced brittle tensile fracture.
摘要翻译：在旋涂玻璃（SOG）被施加并软化固化在具有至少1的高度/宽度纵横比（空间）的金属迹线（10）之后，铝金属迹线选择性地涂覆有选择性钨（16 ）。在将SOG（18）纺丝并软化后，将其回蚀以暴露金属互连。 H 2 O 2中的选择性钨湿蚀刻将SOG从金属壁分离出来，留下淤泥状空隙（20）。现在可以进行无压力的SOG硬化。现在可以施加SOG的覆盖层（22），软化，然后硬化。或者，可以施加其它电介质材料作为覆盖层。此外，通过使用蒸镀氧化物的覆盖层（24'），界面侧壁侧壁空隙（24）可能故意留下未填充。未填充的空隙的介电常数为1.0，这在非常高速的装置中是有用的。所得到的结构在制造时是相对无应力的，并且耐受以后的环境诱导的脆性拉伸断裂。

3. 发明授权

US06608335B2 Grounded fill in a large scale integrated circuit 有权
公开(公告)号：US06608335B2
公开(公告)日：2003-08-19
申请号：US09578919
申请日：2000-05-25
申请人： Pankaj Dixit , Timothy Horel , Mu-Jing Li , Ward Vercruysse
发明人： Pankaj Dixit , Timothy Horel , Mu-Jing Li , Ward Vercruysse
IPC分类号： H01L2710
CPC分类号： H01L21/76838 , H01L21/76819 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit has a plurality of metal layers separated by a plurality of insulating layers. The integrated circuit comprises a pair of conductors on a first metal layer; at least one conductive fill element disposed between the conductors; and a via connecting the fill element to a ground contact on a metal layer adjacent to said first metal layer, where the via is formed of a conductive material.

4. 发明授权

US5322812A Improved method of fabricating antifuses in an integrated circuit device and resulting structure 失效
标题翻译：改进了在集成电路器件中制造反熔丝的方法和结果
公开(公告)号：US5322812A
公开(公告)日：1994-06-21
申请号：US782837
申请日：1991-10-24
申请人： Pankaj Dixit , William P. Ingram, III , Monta R. Holzworth , Richard Klein
发明人： Pankaj Dixit , William P. Ingram, III , Monta R. Holzworth , Richard Klein
IPC分类号： H01L21/82 , H01L21/768 , H01L21/822 , H01L23/525 , H01L27/04 , H01L29/861 , H01L21/70 , H01L27/00
CPC分类号： H01L21/76888 , H01L23/5252 , H01L29/8615 , H01L2924/0002 , Y10S438/935
摘要： Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
摘要翻译：提出了具有硅 - 非晶硅 - 金属层结构的反熔丝的制造的各种改进。包括用于非晶硅层的改进的沉积技术。这些改进包括在不使用铂的情况下制造这种反熔丝的步骤以及由此产生的反熔丝和接触结构。

5. 发明授权

US4884123A Contact plug and interconnect employing a barrier lining and a backfilled conductor material 失效
标题翻译：使用阻挡衬里和回填导体材料的接触插头和互连
公开(公告)号：US4884123A
公开(公告)日：1989-11-28
申请号：US16429
申请日：1987-02-19
申请人： Pankaj Dixit , Jack Sliwa , Richard K. Klein , Craig S. Sander , Mohammad Farnaam
发明人： Pankaj Dixit , Jack Sliwa , Richard K. Klein , Craig S. Sander , Mohammad Farnaam
IPC分类号： H01L29/43 , H01L21/28 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76877 , H01L21/76879 , Y10S257/915
摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry. The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon. The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.

6. 发明授权

US4847674A High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism 失效
$High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism$
标题翻译：高速互连系统，具有难治的非狗骨接触和主动的电迁移抑制机制
公开(公告)号：US4847674A
公开(公告)日：1989-07-11
申请号：US24283
申请日：1987-03-10
申请人： Jack Sliwa , Mohammad Farnaam , Pankaj Dixit , Lewis N. Shen
发明人： Jack Sliwa , Mohammad Farnaam , Pankaj Dixit , Lewis N. Shen
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76886 , H01L23/532 , H01L2924/0002 , Y10S257/90 , Y10S257/915 , Y10T428/12576
摘要： An interconnect (16', 18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surface (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts. In this manner, an interconnect system is provided which has low electrical resistivity but which avoids the much poorer electromigration performance associated with aluminum to aluminum, aluminum to silicon, or aluminum to refractory contact-making as well as with industry-standard bilayer structures comprising refractory/aluminum for interconnect-making.

7. 发明授权

US07096447B1 Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout 有权
标题翻译：用于在复杂的现有电路布局中有效定位和自动校正某些违规的方法和装置
公开(公告)号：US07096447B1
公开(公告)日：2006-08-22
申请号：US10686471
申请日：2003-10-15
申请人： Mu-Jing Li , Suryanarayana R. Maturi , Pankaj Dixit
发明人： Mu-Jing Li , Suryanarayana R. Maturi , Pankaj Dixit
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to locate and correct isolated via rule violations by adding metal features and vias in a respective patch cell associated with each cluster cell. A large complex design is thus divided into cells so that multiple processes can work concurrently as if every process were working on the top level of the design layout.
摘要翻译：示例性CAD设计流程修改现有的大规模芯片布局以加强冗余通路设计规则以提高产量和可靠性。每个金属通孔对从下往上运行，通过在与每个聚集单元相关联的相应补丁单元中添加金属特征和通孔来定位和校正隔离的规则违规。因此，将大型复杂设计分为单元格，以便多个进程同时工作，就好像每个进程在设计布局的顶层工作一样。

8. 发明授权

US5384481A Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof 失效
标题翻译：用于现场可编程门阵列的防漏电路结构及其制造方法
公开(公告)号：US5384481A
公开(公告)日：1995-01-24
申请号：US41924
申请日：1993-04-02
申请人： Monta R. Holzworth , Richard Klein , Pankaj Dixit , William P. Ingram, III
发明人： Monta R. Holzworth , Richard Klein , Pankaj Dixit , William P. Ingram, III
IPC分类号： H01L21/82 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/525 , H01L27/118 , H01L27/02
CPC分类号： H01L23/5252 , H01L21/76888 , H01L2924/0002
摘要： An antifuse structure particularly suitable for field programmable gate arrays is presented. In most present day processes the antifuse structure is formed with a refractory metal layer, amorphous silicon layer and refractory metal layer sandwiched between two metal interconnection lines. Unprogrammed resistances of very high values, programmed resistances of very low values, short programming times and desirable programming voltages are among the advantages realized.
摘要翻译：提出了一种特别适用于现场可编程门阵列的反熔丝结构。在大多数现在的工艺中，反熔丝结构形成有夹在两个金属互连线之间的难熔金属层，非晶硅层和难熔金属层。非常高的值的非编程电阻，非常低的值的编程电阻，短的编程时间和期望的编程电压是实现的优点之一。

9. 发明授权

US4960732A Contact plug and interconnect employing a barrier lining and a backfilled conductor material 失效
标题翻译：使用阻挡衬里和回填导体材料的接触插头和互连
公开(公告)号：US4960732A
公开(公告)日：1990-10-02
申请号：US436399
申请日：1989-11-14
申请人： Pankaj Dixit , Jack Sliwa , Richard K. Klein , Craig S. Sander , Mohammad Farnaam
发明人： Pankaj Dixit , Jack Sliwa , Richard K. Klein , Craig S. Sander , Mohammad Farnaam
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry.The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.
摘要翻译：在通过绝缘层（14）的接触孔（16）中形成稳定的低电阻接触，所述绝缘层（例如，二氧化硅）形成在半导体衬底（12）（例如硅）的表面上，区域（10）。触点包括（a）沿着绝缘层的壁形成并与掺杂区域的部分接触的钛的粘合和接触层（18）; （b）形成在粘附和接触层上的阻挡层（20）; 和（c）导电材料（22），其形成在所述阻挡层上并且至少基本上填充所述接触孔。图案化金属层（26）与其它器件和外部电路形成欧姆接触互连。粘附和接触层和阻挡层物理或化学气相沉积到氧化物表面上。导电层包括CVD或偏置溅射的钨，钼或原位掺杂的CVD多晶硅中的一种。本发明的接触避免了在与其它接触方案相关联的氧化物 - 硅界面和蠕虫孔上侵占的问题，但是保持了工艺简单性。

10. 发明授权

US06499135B1 Computer aided design flow to locate grounded fill in a large scale integrated circuit 有权
标题翻译：计算机辅助设计流程来定位接地填充大规模集成电路
公开(公告)号：US06499135B1
公开(公告)日：2002-12-24
申请号：US09579109
申请日：2000-05-25
申请人： Mu-Jing Li , Ward Vercruysse , Pankaj Dixit , Timothy Horel
发明人： Mu-Jing Li , Ward Vercruysse , Pankaj Dixit , Timothy Horel
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： For an integrated circuit having multiple metal layers, a computer-aided design (CAD) method for designing grounded fill in the integrated circuit includes: (a) finding the eligible fill areas for each metal layer; (b) storing the eligible fill area data for each metal layer in an overflow memory; (c) finding ground contact areas for each metal layer; (d) storing the ground contact area data for each metal layer in an overflow memory; (e) temporarily storing the eligible fill area data for a selected metal layer and the ground contact area data for the metal layers adjacent to the selected metal layer in active memory; (f) fitting a fill pattern to an eligible fill area in the selected metal layer, where the fill pattern is composed of at least one element; (g) checking the adjacent metal layers for a ground contact where the element of the fill pattern may be grounded; (h) locating a conductive via between the element of the fill pattern and a ground contact in an adjacent layer; and (i) repeating steps (e) through (h) for each metal layer.
摘要翻译：对于具有多个金属层的集成电路，用于设计集成电路中的接地填充的计算机辅助设计（CAD）方法包括：（a）找到每个金属层的合格填充区域; （b）将每个金属层的合格填充区域数据存储在溢出存储器中; （c）找出每个金属层的接地面积; （d）将每个金属层的接地面积数据存储在溢出存储器中; （e）临时存储所选择的金属层的合格填充区域数据和与所选金属层相邻的金属层的有源存储器中的接地区域数据; （f）将填充图案拟合到所选择的金属层中的合格填充区域，其中填充图案由至少一个元素组成; （g）检查相邻的金属层以获得填充图案的元件可以接地的接地触点; （h）将填充图案的元件和相邻层中的接地触点之间的导电通孔定位; 和（i）对于每个金属层重复步骤（e）至（h）。

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