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1. 发明申请

US20120286883A1 SYNCHRONIZED OUTPUT OF MULTIPLE RING OSCILLATORS 有权
标题翻译：多环振荡器的同步输出
公开(公告)号：US20120286883A1
公开(公告)日：2012-11-15
申请号：US13107079
申请日：2011-05-13
申请人： Timothy Horel
发明人： Timothy Horel
IPC分类号： H03L7/00
CPC分类号： H03K3/0315
摘要： A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.
摘要翻译：公开了一种用于产生多个环形振荡器的同步输出的电路。在一个实施例中，电路包括被配置为产生第一周期性信号的第一环形振荡器和被配置为产生第二周期信号的第二环形振荡器。电路还可以包括耦合以接收第一周期信号和第二周期信号的选择单元。所述选择单元被配置为响应于来自所述第一和第二周期信号之一的最近接收到的上升沿，将第一时钟沿传送到所述第一和第二环形振荡器的每一个。所述选择单元还被配置为响应于来自所述第一和第二周期信号之一的最近接收的下降沿，将第二时钟沿传送到所述第一和第二环形振荡器中的每一个，其中所述第一和第二时钟沿方向相反。

2. 发明授权

US07529992B1 Configurable integrated circuit with error correcting circuitry 有权
标题翻译：具有纠错电路的可组态集成电路
公开(公告)号：US07529992B1
公开(公告)日：2009-05-05
申请号：US11390973
申请日：2006-03-27
申请人： Steven Teig , Jason Redgrave , Timothy Horel
发明人： Steven Teig , Jason Redgrave , Timothy Horel
IPC分类号： G01R31/28
CPC分类号： G06F11/1008 , G11C2029/0411 , H03K19/17752 , H03K19/17764
摘要： An integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data and error correction data, and error correction circuitry for receiving the configuration data, correcting a particular error in the received configuration data when the particular error exists in the configuration data, and outputting the configuration data without the particular error. The IC further includes a configurable circuit (e.g., a configurable logic circuit or a configurable interconnect circuit) that receives the error-corrected configuration data from the error correction circuitry, and circuitry to write the corrected configuration data and error data back into the configuration memory.
摘要翻译：集成电路（IC）对配置数据执行错误检测和校正。 IC包括用于存储配置数据和纠错数据的配置存储器，以及用于接收配置数据的纠错电路，当配置数据中存在特定错误时校正接收到的配置数据中的特定错误，并且输出配置数据而没有特定的错误。 IC还包括从纠错电路接收经纠错的配置数据的可配置电路（例如，可配置逻辑电路或可配置互连电路），以及将校正后的配置数据和错误数据写入配置存储器的电路。

3. 发明授权

US06499135B1 Computer aided design flow to locate grounded fill in a large scale integrated circuit 有权
标题翻译：计算机辅助设计流程来定位接地填充大规模集成电路
公开(公告)号：US06499135B1
公开(公告)日：2002-12-24
申请号：US09579109
申请日：2000-05-25
申请人： Mu-Jing Li , Ward Vercruysse , Pankaj Dixit , Timothy Horel
发明人： Mu-Jing Li , Ward Vercruysse , Pankaj Dixit , Timothy Horel
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： For an integrated circuit having multiple metal layers, a computer-aided design (CAD) method for designing grounded fill in the integrated circuit includes: (a) finding the eligible fill areas for each metal layer; (b) storing the eligible fill area data for each metal layer in an overflow memory; (c) finding ground contact areas for each metal layer; (d) storing the ground contact area data for each metal layer in an overflow memory; (e) temporarily storing the eligible fill area data for a selected metal layer and the ground contact area data for the metal layers adjacent to the selected metal layer in active memory; (f) fitting a fill pattern to an eligible fill area in the selected metal layer, where the fill pattern is composed of at least one element; (g) checking the adjacent metal layers for a ground contact where the element of the fill pattern may be grounded; (h) locating a conductive via between the element of the fill pattern and a ground contact in an adjacent layer; and (i) repeating steps (e) through (h) for each metal layer.
摘要翻译：对于具有多个金属层的集成电路，用于设计集成电路中的接地填充的计算机辅助设计（CAD）方法包括：（a）找到每个金属层的合格填充区域; （b）将每个金属层的合格填充区域数据存储在溢出存储器中; （c）找出每个金属层的接地面积; （d）将每个金属层的接地面积数据存储在溢出存储器中; （e）临时存储所选择的金属层的合格填充区域数据和与所选金属层相邻的金属层的有源存储器中的接地区域数据; （f）将填充图案拟合到所选择的金属层中的合格填充区域，其中填充图案由至少一个元素组成; （g）检查相邻的金属层以获得填充图案的元件可以接地的接地触点; （h）将填充图案的元件和相邻层中的接地触点之间的导电通孔定位; 和（i）对于每个金属层重复步骤（e）至（h）。

4. 发明授权

US08395454B2 Synchronized output of multiple ring oscillators 有权
标题翻译：多个环形振荡器的同步输出
公开(公告)号：US08395454B2
公开(公告)日：2013-03-12
申请号：US13107079
申请日：2011-05-13
申请人： Timothy Horel
发明人： Timothy Horel
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.
摘要翻译：公开了一种用于产生多个环形振荡器的同步输出的电路。在一个实施例中，电路包括被配置为产生第一周期性信号的第一环形振荡器和被配置为产生第二周期信号的第二环形振荡器。电路还可以包括耦合以接收第一周期信号和第二周期信号的选择单元。所述选择单元被配置为响应于来自所述第一和第二周期信号之一的最近接收到的上升沿，将第一时钟沿传送到所述第一和第二环形振荡器的每一个。所述选择单元还被配置为响应于来自所述第一和第二周期信号之一的最近接收的下降沿，将第二时钟沿传送到所述第一和第二环形振荡器中的每一个，其中所述第一和第二时钟沿方向相反。

5. 发明授权

US06608335B2 Grounded fill in a large scale integrated circuit 有权
公开(公告)号：US06608335B2
公开(公告)日：2003-08-19
申请号：US09578919
申请日：2000-05-25
申请人： Pankaj Dixit , Timothy Horel , Mu-Jing Li , Ward Vercruysse
发明人： Pankaj Dixit , Timothy Horel , Mu-Jing Li , Ward Vercruysse
IPC分类号： H01L2710
CPC分类号： H01L21/76838 , H01L21/76819 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit has a plurality of metal layers separated by a plurality of insulating layers. The integrated circuit comprises a pair of conductors on a first metal layer; at least one conductive fill element disposed between the conductors; and a via connecting the fill element to a ground contact on a metal layer adjacent to said first metal layer, where the via is formed of a conductive material.

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