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1. 发明授权

US6035390A Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation 失效
标题翻译：用于与执行算术或逻辑运算同时产生和逻辑组合小于（LT），大于（GT）和等于（EQ））条件码位的方法和装置
公开(公告)号：US6035390A
公开(公告)日：2000-03-07
申请号：US5471
申请日：1998-01-12
申请人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
发明人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F9/38 , G06F7/48 , G06F9/302 , G06F9/305 , G06F9/32 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/48 , G06F9/30094
摘要： A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.
摘要翻译：处理器至少包括一个执行单元，该执行单元通过使用一个或多个操作数和条件代码逻辑执行指令所指示的操作来执行指令，所述操作数和条件代码逻辑确定小于，大于和等于与执行同时执行的指令相关联的条件代码位的执行单元的指令。在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。

2. 发明授权

US06212619B1 System and method for high-speed register renaming by counting 失效
标题翻译：通过计数高速寄存器重命名的系统和方法，使用具有飞行中每条指令的寄存器位的表
公开(公告)号：US06212619B1
公开(公告)日：2001-04-03
申请号：US09075918
申请日：1998-05-11
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F1500
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates a list of tags corresponding to specific registers that are not in use during loading of a given instruction. A table is constructed having one bit for each register per instruction in flight. The entries in the table may be combined in a logical OR fashion to create a vector that identifies which registers are in use by instructions that are in flight. Validity bits can also be generated to indicate validity of the generated tags, wherein a generated tag is invalid only if an insufficient number of registers are available during loading of the given instruction. The execution units are preferably pipelined.
摘要翻译：一种用于执行无序指令的超标量计算机体系结构，包括多个执行单元，多个寄存器和寄存器重命名电路，该电路生成与给定的加载期间不使用的特定寄存器相对应的标签列表指令。在飞行中每个指令的每个寄存器构造一个表。表中的条目可以以逻辑或或者方式组合，以创建一个向量，用于识别正在飞行中的指令使用哪些寄存器。也可以生成有效位以指示生成的标签的有效性，其中仅当在给定指令的加载期间没有足够数量的寄存器可用时，所生成的标签才是无效的。执行单元优选地被流水线化。

3. 发明授权

US6014763A At-speed scan testing 失效
标题翻译：高速扫描测试
公开(公告)号：US6014763A
公开(公告)日：2000-01-11
申请号：US7670
申请日：1998-01-15
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
摘要翻译：通过将并行扫描输入（扫描数据和扫描控制）转换为串行扫描来扫描集成电路的方法，将串行扫描输入通过扫描电路传送以创建串行扫描输出，将扫描输出从串行转换为并行转换，从集成电路并行扫描输出到测试仪。通过将测试仪与集成电路的分频时钟信号（1 / N）同步，得到测试仪时钟信号。通信以测试仪时钟信号的速度进行，但扫描以被测设备的全部操作速度运行。对于超过1 GHz的速度，可以实现高速扫描测试。

4. 发明授权

US07493357B2 Random carry-in for floating-point operations 有权
标题翻译：随机进位浮点运算
公开(公告)号：US07493357B2
公开(公告)日：2009-02-17
申请号：US10971851
申请日：2004-10-22
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
IPC分类号： G06F7/44 , G06F7/38
CPC分类号： G06F7/485 , G06F7/49947
摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.
摘要翻译：一种用于对浮点操作数进行相加和相乘以产生固定大小的尾数结果的方法和装置。根据本加法，第一浮点数操作数的尾数根据相对操作数指数信息移位。接下来，将第一操作数尾数添加到第二操作数尾数。所述添加步骤包括用随机生成的进位位替换第一操作数尾数的最不重要的非重叠部分。根据乘法方法，从一对浮点运算符尾数生成部分乘积数组。接下来，在将部分乘积阵列压缩为压缩尾数结果之前，将部分乘积阵列的低阶位部分替换为随机生成的进位值。

5. 发明授权

US07225422B2 Wire trimmed programmable logic array 有权
标题翻译：电线修剪可编程逻辑阵列
公开(公告)号：US07225422B2
公开(公告)日：2007-05-29
申请号：US10464879
申请日：2003-06-19
申请人： Robert John Bucki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Robert John Bucki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.
摘要翻译：设计逻辑电路的方法包括提供具有至少一个晶体管的叶单元。叶片适用于逻辑电路中的1单元或0单元。使用至少一个1-单元和至少一个O单元来平铺第一对接叶单元阵列以通过阵列单元的相对位置限定至少一个逻辑表达式。长度优化的互连将添加到阵列中。每个长度优化的互连终止于互连接触到的阵列中的最后一个叶单元格。叶细胞可以是浮叶细胞，其中任何一对邻接细胞彼此电隔离，直到长度优化的互连被添加到设计中。叶单元阵列可能包括一组行和一组列，其中每行中的叶单元和列组各自对应于逻辑表达式的输入。

6. 发明授权

US06941335B2 Random carry-in for floating-point operations 失效
公开(公告)号：US06941335B2
公开(公告)日：2005-09-06
申请号：US09999135
申请日：2001-11-29
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
IPC分类号： G06F7/38 , G06F7/42 , G06F7/485 , G06F7/499 , G06F17/10
CPC分类号： G06F7/485 , G06F7/49947
摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

7. 发明授权

US06825695B1 Unified local clock buffer structures 失效
标题翻译：统一本地时钟缓冲结构
公开(公告)号：US06825695B1
公开(公告)日：2004-11-30
申请号：US10455170
申请日：2003-06-05
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： H03K19096
CPC分类号： G06F1/10
摘要： Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.
摘要翻译：公开了几个本地时钟缓冲器，每个本地时钟缓冲器包括输入部分和输出部分。输入部分基本相同，包括控制逻辑和门控逻辑。控制逻辑产生取决于多个控制信号和时间延迟的全局时钟信号的选通信号。门控逻辑产生取决于全局时钟信号和门控信号的中间时钟信号。输出部分根据中间时钟信号产生至少一个本地时钟信号。在一个实施例中，输出部分产生取决于中间时钟信号的第一本地时钟信号和取决于第一本地时钟信号的第二本地时钟信号。在另一个实施例中，选通逻辑根据全局时钟和门控信号以及反馈信号产生中间时钟信号。输出部分产生反馈信号和一个或多个本地时钟信号。

8. 发明授权

US06356990B1 Set-associative cache memory having a built-in set prediction array 有权
标题翻译：具有内置集预测阵列的组相关高速缓冲存储器
公开(公告)号：US06356990B1
公开(公告)日：2002-03-12
申请号：US09496474
申请日：2000-02-02
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
IPC分类号： G06F1208
CPC分类号： G06F12/1054 , G06F12/0864 , G06F2212/6082 , Y02D10/13
摘要： A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.
摘要翻译：公开了一种具有内置设置预测阵列的组合高速缓存存储器。可以通过具有标签字段，行索引字段和字节字段的有效地址访问高速缓冲存储器。高速缓冲存储器包括目录，存储器阵列，翻译后备缓冲器和设置预测阵列。存储器阵列与目录相关联，使得目录中的每个标签条目对应于存储器阵列内的高速缓存行。响应于通过有效地址的高速缓存访问，转换后备缓冲器确定与有效地址相关联的数据是否存储在存储器阵列内。集合预测阵列内置在存储器阵列内，使得可以在与存储器阵列内的高速缓存行的访问相同的访问周期中执行对集合预测阵列内的行条目的访问。

9. 发明授权

US6104213A Domino logic circuit having a clocked precharge 失效
标题翻译：多米诺逻辑电路具有时钟预充电
公开(公告)号：US6104213A
公开(公告)日：2000-08-15
申请号：US32820
申请日：1998-03-02
申请人： Sang Hoo Dhong , Uttam Shyamalindu Ghoshal , Joel Abraham Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Uttam Shyamalindu Ghoshal , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K19/096 , H03K3/01 , H03K19/0175
CPC分类号： H03K19/0963
摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharger transistor, several input transistors, and an invertor. Connected to a power supply, the precharge transistor receives a first clock input. The discharge transistor, connected to the ground, receives a second clock input. The input transistors is coupled between the precharge transistor and the discharge transistor. Each of the input transistors receives a signal input. The inverter has an input coupled to the precharge transistor, and an output to yield a signal output. The inverter includes a first transistor and a second transistor connected in series, and the output of the inverter is connected to a body of the first transistor.
摘要翻译：公开了具有时钟预充电的多米诺骨牌逻辑电路。多米诺逻辑电路包括预充电晶体管，放电晶体管，多个输入晶体管和反相器。连接到电源，预充电晶体管接收第一时钟输入。连接到地的放电晶体管接收第二个时钟输入。输入晶体管耦合在预充电晶体管和放电晶体管之间。每个输入晶体管接收信号输入。反相器具有耦合到预充电晶体管的输入端和产生信号输出的输出端。逆变器包括串联连接的第一晶体管和第二晶体管，反相器的输出端连接到第一晶体管的主体。

10. 发明授权

US6021461A Method for reducing power consumption in a set associative cache memory system 失效
标题翻译：一种用于降低组合高速缓冲存储器系统中功耗的方法
公开(公告)号：US6021461A
公开(公告)日：2000-02-01
申请号：US244079
申请日：1999-02-04
申请人： Sang Hoo Dhong , Philip George Emma , William Robert Reohr , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Philip George Emma , William Robert Reohr , Joel Abraham Silberman
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0879 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , Y02B60/1225
摘要： A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The method also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.
摘要翻译：一种用于访问有助于增加并存储请求的高速缓冲存储器的方法，从而使应用的基地址请求通过使用内置在存储器解码电路中的内部地址生成设备来增加高速缓存的带宽。引入内部地址生成工具简化了内置于内存系统中的典型请求者的无关控制。该方法还可以减少利用存储器内部地址生成设备的请求所消耗的功耗。通过在增量提取期间启用一组读出放大器，集合的联想高速缓冲存储器系统中的功耗进一步降低。

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