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    • 1. 发明授权
    • Wire trimmed programmable logic array
    • 电线修剪可编程逻辑阵列
    • US07225422B2
    • 2007-05-29
    • US10464879
    • 2003-06-19
    • Robert John BuckiSang Hoo DhongJoel Abraham SilbermanOsamu Takahashi
    • Robert John BuckiSang Hoo DhongJoel Abraham SilbermanOsamu Takahashi
    • G06F17/50
    • G06F17/5054
    • A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.
    • 设计逻辑电路的方法包括提供具有至少一个晶体管的叶单元。 叶片适用于逻辑电路中的1单元或0单元。 使用至少一个1-单元和至少一个O单元来平铺第一对接叶单元阵列以通过阵列单元的相对位置限定至少一个逻辑表达式。 长度优化的互连将添加到阵列中。 每个长度优化的互连终止于互连接触到的阵列中的最后一个叶单元格。 叶细胞可以是浮叶细胞,其中任何一对邻接细胞彼此电隔离,直到长度优化的互连被添加到设计中。 叶单元阵列可能包括一组行和一组列,其中每行中的叶单元和列组各自对应于逻辑表达式的输入。