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1. 发明授权

US07493357B2 Random carry-in for floating-point operations 有权
标题翻译：随机进位浮点运算
公开(公告)号：US07493357B2
公开(公告)日：2009-02-17
申请号：US10971851
申请日：2004-10-22
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
IPC分类号： G06F7/44 , G06F7/38
CPC分类号： G06F7/485 , G06F7/49947
摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.
摘要翻译：一种用于对浮点操作数进行相加和相乘以产生固定大小的尾数结果的方法和装置。根据本加法，第一浮点数操作数的尾数根据相对操作数指数信息移位。接下来，将第一操作数尾数添加到第二操作数尾数。所述添加步骤包括用随机生成的进位位替换第一操作数尾数的最不重要的非重叠部分。根据乘法方法，从一对浮点运算符尾数生成部分乘积数组。接下来，在将部分乘积阵列压缩为压缩尾数结果之前，将部分乘积阵列的低阶位部分替换为随机生成的进位值。

2. 发明授权

US06941335B2 Random carry-in for floating-point operations 失效
公开(公告)号：US06941335B2
公开(公告)日：2005-09-06
申请号：US09999135
申请日：2001-11-29
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin Nowka , Steven Douglas Posluszny , Joel Abraham Silberman
IPC分类号： G06F7/38 , G06F7/42 , G06F7/485 , G06F7/499 , G06F17/10
CPC分类号： G06F7/485 , G06F7/49947
摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

3. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

4. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

5. 发明授权

US6038659A Method for using read-only memory to generate controls for microprocessor 失效
标题翻译：使用只读存储器生成微处理器控制的方法
公开(公告)号：US6038659A
公开(公告)日：2000-03-14
申请号：US968120
申请日：1997-11-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/382 , G06F9/30145 , G06F9/30196
摘要： A circuit for generating control signals used in a microprocessor has a storage array, such as a read-only memory (ROM) array, which contains a plurality of predefined logic patterns. An entry of the ROM array is selected, such as by the use of an address decoder, to choose a specific pattern, and the specific pattern is then modified based on a dynamic signal to generate an output control signal. The microprocessor may further predecode a base instruction using operation and operand source bits to yield a predecoded instruction having an address field whose value corresponds to the specific pattern. The dynamic signal can be based on whether an operand should be forwarded from a microprocessor component, and the specific pattern is then equivalent to a value for control signals required to execute an instruction when assuming that the operand should not be forwarded. Special control states can also be implemented, such as stall, halt, or scan data, through the use of particular code points in the ROM.
摘要翻译：用于产生在微处理器中使用的控制信号的电路具有存储阵列，诸如只读存储器（ROM）阵列，其包含多个预定逻辑模式。选择ROM阵列的入口，例如通过使用地址解码器来选择特定模式，然后基于动态信号修改特定模式以产生输出控制信号。微处理器可以进一步使用操作和源位来对基本指令进行预解码，以产生具有对应于特定模式的地址字段的预解码指令。动态信号可以基于操作数是否应该从微处理器组件转发，并且特定模式然后等于假设不应该转发操作数时执行指令所需的控制信号的值。还可以通过使用ROM中的特定代码点来实现特殊控制状态，例如停止，停止或扫描数据。

6. 发明授权

US08136061B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US08136061B2
公开(公告)日：2012-03-13
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

7. 发明授权

US06600959B1 Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays 失效
标题翻译：使用动态可编程逻辑阵列实现微处理器控制逻辑的方法和装置
公开(公告)号：US06600959B1
公开(公告)日：2003-07-29
申请号：US09498934
申请日：2000-02-04
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G05B1918
CPC分类号： H03K17/693 , H03K5/06
摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.
摘要翻译：在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

8. 发明授权

US06502224B2 Method and apparatus for synthesizing levelized logic 失效
标题翻译：用于合成等级化逻辑的方法和装置
公开(公告)号：US06502224B2
公开(公告)日：2002-12-31
申请号：US09833413
申请日：2001-04-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5054 , Y02T10/82
摘要： A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.
摘要翻译：公开了一种用于合成具有同步输出的逻辑电路的方法和装置。逻辑设计者选择固定数量的电平来合成电路，每个级别实现多个具有相同传播延迟的不同逻辑功能。通过确保每个逻辑功能通过将逻辑功能从电平连接到电平来合成，使得每个信号路径通过每个级别一次且仅一次，从而同步电路输出。

9. 发明授权

US06212619B1 System and method for high-speed register renaming by counting 失效
标题翻译：通过计数高速寄存器重命名的系统和方法，使用具有飞行中每条指令的寄存器位的表
公开(公告)号：US06212619B1
公开(公告)日：2001-04-03
申请号：US09075918
申请日：1998-05-11
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F1500
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates a list of tags corresponding to specific registers that are not in use during loading of a given instruction. A table is constructed having one bit for each register per instruction in flight. The entries in the table may be combined in a logical OR fashion to create a vector that identifies which registers are in use by instructions that are in flight. Validity bits can also be generated to indicate validity of the generated tags, wherein a generated tag is invalid only if an insufficient number of registers are available during loading of the given instruction. The execution units are preferably pipelined.
摘要翻译：一种用于执行无序指令的超标量计算机体系结构，包括多个执行单元，多个寄存器和寄存器重命名电路，该电路生成与给定的加载期间不使用的特定寄存器相对应的标签列表指令。在飞行中每个指令的每个寄存器构造一个表。表中的条目可以以逻辑或或者方式组合，以创建一个向量，用于识别正在飞行中的指令使用哪些寄存器。也可以生成有效位以指示生成的标签的有效性，其中仅当在给定指令的加载期间没有足够数量的寄存器可用时，所生成的标签才是无效的。执行单元优选地被流水线化。

10. 发明授权

US6138208A Multiple level cache memory with overlapped L1 and L2 memory access 失效
标题翻译：具有重叠的L1和L2存储器访问的多级高速缓存
公开(公告)号：US6138208A
公开(公告)日：2000-10-24
申请号：US59000
申请日：1998-04-13
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0884
摘要： A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.
摘要翻译：提供对多个高速缓存级别的同时或重叠访问以减少对于较高级别的高速缓存未命中的延迟损失的方法。处理器发出值（数据或指令）的请求，并且在确定高速缓存的较高级别是否发生了该值的高速缓存未命中之前被转发到高速缓存的较低级。在其中较低级别是L2高速缓存的实施例中，L2高速缓存可以将该值直接提供给处理器。地址解码器在高速缓存的较高级并行操作以满足多个同时的存储器请求。其中一个地址（由基于来自高速缓存的较高级别的命中/未命中信息的优先级逻辑选择）由多路复用器选通到高速缓存的较低级的多个存储器阵列字线驱动器。可以立即解码地址中的一些不需要虚拟到实际转换的位。

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