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1. 发明授权

US06356990B1 Set-associative cache memory having a built-in set prediction array 有权
标题翻译：具有内置集预测阵列的组相关高速缓冲存储器
公开(公告)号：US06356990B1
公开(公告)日：2002-03-12
申请号：US09496474
申请日：2000-02-02
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
IPC分类号： G06F1208
CPC分类号： G06F12/1054 , G06F12/0864 , G06F2212/6082 , Y02D10/13
摘要： A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.
摘要翻译：公开了一种具有内置设置预测阵列的组合高速缓存存储器。可以通过具有标签字段，行索引字段和字节字段的有效地址访问高速缓冲存储器。高速缓冲存储器包括目录，存储器阵列，翻译后备缓冲器和设置预测阵列。存储器阵列与目录相关联，使得目录中的每个标签条目对应于存储器阵列内的高速缓存行。响应于通过有效地址的高速缓存访问，转换后备缓冲器确定与有效地址相关联的数据是否存储在存储器阵列内。集合预测阵列内置在存储器阵列内，使得可以在与存储器阵列内的高速缓存行的访问相同的访问周期中执行对集合预测阵列内的行条目的访问。

2. 发明授权

US06453390B1 Processor cycle time independent pipeline cache and method for pipelining data from a cache 有权
标题翻译：处理器周期时间独立的流水线缓存和从缓存流水线数据的方法
公开(公告)号：US06453390B1
公开(公告)日：2002-09-17
申请号：US09458405
申请日：1999-12-10
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0859 , G06F12/0893
摘要： A processor cycle time independent pipeline cache and method for pipelining data from a cache provide a processor with operand data and instructions without introducing additional latency for synchronization when processor frequency is lowered or when a reload port provides a value a cycle earlier than a read access from the cache storage. The cache incorporates a persistent data bus that synchronizes the stored data access with the pipeline and can also utilize bypass mode data available from a cache input from the lower level when data is being written to the cache.
摘要翻译：处理器周期时间独立的流水线高速缓存和用于从高速缓存流水线提供数据的方法为处理器提供操作数数据和指令，而不会在处理器频率降低时引入额外的同步延迟，或者当重新加载端口提供比读取访问更早的值时缓存存储。高速缓存包括持久性数据总线，其将存储的数据访问与流水线同步，并且当数据被写入高速缓存时，还可以使用从较低级别的高速缓存输入中可用的旁路模式数据。

3. 发明授权

US06239620B1 Method and apparatus for generating true/complement signals 失效
标题翻译：用于产生真/补补信号的方法和装置
公开(公告)号：US06239620B1
公开(公告)日：2001-05-29
申请号：US09450982
申请日：1999-11-29
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
IPC分类号： H03K33568
CPC分类号： H03K5/151
摘要： A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.
摘要翻译：公开了一种具有动态节点的动态逻辑电路的真/补信号发生器。具有动态节点的动态逻辑电路的真/补信号发生器包括级联反相器电路，第一半锁存电路和第二半锁存电路。连接到动态节点的级联逆变器电路包括与第二反相器串联连接的第一反相器。连接到级联逆变器电路的第二反相器的输出端，第一半锁存电路产生输出信号。连接到级联逆变器电路的第一反相器的输出端，第二半锁存电路产生补码输出信号。

4. 发明授权

US5771268A High speed rotator with array method 失效
标题翻译：高速旋转器阵列法
公开(公告)号：US5771268A
公开(公告)日：1998-06-23
申请号：US762910
申请日：1996-12-10
申请人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
发明人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
IPC分类号： G11C19/38 , G11C19/00
CPC分类号： G11C19/38
摘要： A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.
摘要翻译：用于将输入数据移位一定量的高速旋转器阵列。旋转器阵列包括跨越阵列延伸的多个直移位控制线，用于接收代表移位值的移位数据，以及多个用于接收要移位的输入数据的输入端。旋转器阵列还包括耦合到多个输入端子的多条数据线，跨越阵列沿对角线和水平方向延伸。响应于接收到移位数据和输入数据的旋转体阵列，多个输出端子发送移位的输出数据。

5. 发明授权

US06453258B1 Optimized burn-in for fixed time dynamic logic circuitry 失效
标题翻译：固定时间动态逻辑电路的优化老化
公开(公告)号：US06453258B1
公开(公告)日：2002-09-17
申请号：US09465176
申请日：1999-12-17
申请人： Naoaki Aoki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Naoaki Aoki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F104
CPC分类号： G01R31/2856
摘要： A system and method for ensuring comprehensive testing coverage of components within a dynamic logic macro during a burn-in test cycle. Burn-in testing is initiated within dynamic logic circuit having a dynamic logic block and a self-reset loop for generating a reset signal. A multiple phase burn-in test input is applied to the self-reset loop for modifying the duration of the reset signal during burn-in testing, such that the components within the dynamic logic macro are adequately stressed during the burn-in test cycle.
摘要翻译：一种用于在老化测试周期内确保动态逻辑宏中组件的全面测试覆盖的系统和方法。在具有动态逻辑块和用于产生复位信号的自复位环路的动态逻辑电路内启动老化测试。多次老化测试输入被应用于自复位环路，用于在老化测试期间修改复位信号的持续时间，使得在老化测试周期期间动态逻辑宏中的组件被充分应力。

6. 发明授权

US5877972A High speed incrementer with array method 失效
标题翻译：具有阵列方法的高速增量器
公开(公告)号：US5877972A
公开(公告)日：1999-03-02
申请号：US783979
申请日：1997-01-15
申请人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
发明人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
IPC分类号： G06F7/38 , G06F7/50 , G06F7/505 , G06F7/508
CPC分类号： G06F7/5055
摘要： A high-speed incrementer array for incrementing a data input value by a binary one, wherein the data input value comprises a plurality of input bit values. The incrementer array includes a plurality of word lines, bit-line pairs, and sense amplifiers. The input bit values are received as a plurality of complement input signals and a plurality of true input signals. The complement input signals are transmitted on the plurality of word lines that form the rows of the array. Each one of plurality of bit-line pairs is located in a respective column of the array and is coupled to particular ones of the word lines in the rows of the array. Each one of the plurality of sense amplifiers is coupled to a respective bit-line pair for sensing a voltage difference between the bit-line pair, such that the bit-line pair and the sense amplifier perform a logical NOR of the complement input signals to produce a NOR output. Each one of the plurality of exclusive-or gates is coupled to a respective NOR output and to a particular one of the true input signals for generating an incremented output signal.
摘要翻译：一种用于将数据输入值递增二进制数据的高速递增器阵列，其中数据输入值包括多个输入位值。增量器阵列包括多个字线，位线对和读出放大器。输入位值被接收为多个补码输入信号和多个真实输入信号。补码输入信号在形成阵列行的多条字线上传输。多个位线对中的每一个位于阵列的相应列中并且耦合到阵列的行中的特定字线。多个读出放大器中的每一个耦合到相应的位线对，用于感测位线对之间的电压差，使得位线对和读出放大器执行补码输入信号的逻辑或产生NOR输出。多个异或门中的每一个被耦合到相应的或非输出和真实输入信号中的特定一个以产生增加的输出信号。

7. 发明授权

US06584485B1 4 to 2 adder 失效
标题翻译： 4〜2加法器
公开(公告)号：US06584485B1
公开(公告)日：2003-06-24
申请号：US09549766
申请日：2000-04-14
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Ohsang Kwon
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Ohsang Kwon
IPC分类号： G06F750
CPC分类号： G06F7/509 , G06F7/5016
摘要： A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.
摘要翻译：公开了一种四输入到双输出加法器。四输入/双输出加法器包括总和全加器和修正全加器。总和前置全加器包括一个XOR3块和一个AXOR块，用于接收来自正向相邻加法器的第一输入，第二输入，第三输入和输入，以产生第一和信号和总和前进进位信号，分别。修改后的全加器包括一个XOR2块和一个MUX2块，用于从后向相邻加法器接收来自和 - 全码头全加器的第一和信号，以及来自后向相邻加法器的和 - 总括进位信号，以产生第二和信号，一个进位信号。

8. 发明申请

US20060285418A1 Semiconductor integrated circuit device, electronic component mounting board and layout designing method for the semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件，电子元件安装板和半导体集成电路器件的布局设计方法
公开(公告)号：US20060285418A1
公开(公告)日：2006-12-21
申请号：US11450514
申请日：2006-06-12
申请人： Naoaki Aoki
发明人： Naoaki Aoki
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , H01L23/5286 , H01L24/06 , H01L2224/05554 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A circuit configuration is adopted which supplies an internal power supply voltage from outside and inside of a semiconductor chip 1. The internal power supply voltage from the outside is supplied through an internal power supply pad 20, whereas the internal power supply voltage from the inside is supplied through a regulator 110. The regulator 110 is arranged in an area giving a remarkable level reduction due to the voltage drop in an internal power supply wiring 21a, thereby supplementing shortage in the internal power supply voltage from the internal power supply pad 20.
摘要翻译：采用从半导体芯片1的外部和内部提供内部电源电压的电路结构。通过内部电源焊盘20提供来自外部的内部电源电压，而来自内部的内部电源电压调节器110被布置在由于内部电源布线21a的电压降而引起显着的电平降低的区域中，从而补充来自内部电源焊盘20的内部电源电压的不足。

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