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    • 1. 发明授权
    • Semiconductor structure and method for manufacturing the same
    • 半导体结构及其制造方法
    • US09419108B2
    • 2016-08-16
    • US14406904
    • 2012-08-17
    • Qingqing LiangHuicai ZhongHuilong ZhuChao ZhaoTianchun Ye
    • Qingqing LiangHuicai ZhongHuilong ZhuChao ZhaoTianchun Ye
    • H01L29/66H01L29/78
    • H01L29/66795H01L29/785H01L29/7855
    • One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
    • 本发明的一个实施例提供了一种用于制造半导体结构的方法,其包括:在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域,以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。
    • 2. 发明申请
    • METHOD FOR MANUFACTURING P-TYPE MOSFET
    • 制造P型MOSFET的方法
    • US20150295067A1
    • 2015-10-15
    • US14004802
    • 2012-12-07
    • Qiuxia XuHuilong ZhuHuajie ZhouGaobo XuQingqing Liang
    • Qiuxia XuHuilong ZhuHuajie ZhouGaobo XuQingqing Liang
    • H01L29/66H01L21/28H01L29/423H01L29/51H01L21/02H01L21/265H01L29/49
    • H01L29/66545H01L21/02181H01L21/02189H01L21/02192H01L21/02194H01L21/265H01L21/28088H01L21/28185H01L21/3215H01L29/42364H01L29/49H01L29/4966H01L29/517H01L29/518H01L29/7833
    • The present disclosure discloses a method for manufacturing a P-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
    • 本公开公开了一种用于制造P型MOSFET的方法,包括:在半导体衬底上形成MOSFET的一部分,所述MOSFET的部分包括半导体衬底中的源/漏区,源极/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入到第一金属栅极层中; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚,并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。
    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US09012963B2
    • 2015-04-21
    • US13501518
    • 2011-11-18
    • Qingqing LiangMiao XuHuilong ZhuHuicai Zhong
    • Qingqing LiangMiao XuHuilong ZhuHuicai Zhong
    • H01L29/66H01L29/786H01L29/49
    • H01L29/78654H01L29/4908H01L29/78603H01L29/78648H01L29/78696
    • The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.
    • 本申请公开了一种半导体器件,其包括超薄半导体层中的源极区域和漏极区域; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠,所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠,所述背栅叠层包括在所述背栅极和沟道区域之间的背栅极和背栅电介质,其中所述前栅极由高Vt材料制成,并且所述背栅极 由低Vt材料制成。 根据另一实施例,前栅极和后栅极由相同的材料制成,并且背栅在工作期间被施加正偏压。 半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。
    • 4. 发明授权
    • Fin field-effect transistor and method for manufacturing the same
    • 翅片场效应晶体管及其制造方法
    • US08859378B2
    • 2014-10-14
    • US13377141
    • 2011-08-10
    • Qingqing LiangHuicai ZhongHuilong Zhu
    • Qingqing LiangHuicai ZhongHuilong Zhu
    • H01L21/336H01L27/12H01L21/8234H01L21/84H01L27/088H01L29/66
    • H01L27/1211H01L21/823431H01L21/845H01L27/0886H01L29/66545
    • Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.
    • 本发明的实施例公开了一种制造Fin场效应晶体管的方法。 当形成翅片时,在翅片上形成跨鳍片的虚拟栅极,在虚拟栅极的侧壁上形成间隔物,并且在第一介电层上形成覆盖层,并在模拟栅极外部形成覆盖层, 间隔物 然后,通过间隔件在虚拟栅极的两侧形成自对准和升高的源极/漏极区域,其中栅极和源极/漏极区域的上表面在同一平面内。 栅极和源极/漏极区域的上表面位于相同的平面中,使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开,从而提高对准精度,解决接触插塞的不准确的对准以及提高器件AC性能。
    • 8. 发明授权
    • MOSFET
    • US08716799B2
    • 2014-05-06
    • US13376996
    • 2011-08-01
    • Huilong ZhuMiao XuQingqing Liang
    • Huilong ZhuMiao XuQingqing Liang
    • H01L27/01H01L27/12H01L31/0392
    • H01L29/78648H01L21/2652
    • The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate.
    • 本申请公开了一种MOSFET及其制造方法,其中,所述MOSFET包括:SOI晶片,其包含半导体基板,埋入绝缘体层和半导体层,所述埋入绝缘体层设置在所述半导体基板上, 并且所述半导体层设置在所述埋入绝缘体层上; 栅极堆叠,其设置在半导体层上; 源极区域和漏极区域,其设置在所述半导体层中并且在所述栅极堆叠的相对侧上; 以及沟道区域,其设置在所述半导体层中并且被所述源极区域和所述漏极区域夹持,其中所述MOSFET还包括设置在所述半导体衬底中的背栅极,并且其中所述后栅极包括第一,第二和第三补偿掺杂 第一补偿掺杂区域设置在源极区域和漏极区域下方; 所述第二补偿掺杂区域在远离所述沟道区域并邻接所述第一补偿掺杂区域的方向上延伸; 并且第三补偿掺杂区域设置在沟道区域的下方并与第一补偿掺杂区域相邻。 通过改变背栅的掺杂类型,MOSFET可以具有可调的阈值电压,并且可以具有减小的寄生电容和与后栅极相关联的降低的接触电阻。
    • 9. 发明申请
    • SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20140027864A1
    • 2014-01-30
    • US13578872
    • 2012-05-18
    • Huilong ZhuQingqing LiangHuicai Zhong
    • Huilong ZhuQingqing LiangHuicai Zhong
    • H01L21/336H01L29/78
    • H01L29/6659H01L29/66659H01L29/7835
    • Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.
    • 公开了半导体装置及其制造方法。 在一个实施例中,该方法包括:在衬底上形成第一屏蔽层,并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层,并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层,以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。