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1. 发明授权

US09252280B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US09252280B2
公开(公告)日：2016-02-02
申请号：US13510461
申请日：2011-11-18
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/66742 , H01L29/78609
摘要： The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.
摘要翻译：本公开公开了一种金属氧化物半导体场效应晶体管（MOSFET）及其制造方法。所述MOSFET包括：绝缘体上硅（SOI）晶片，其包含半导体衬底，掩埋绝缘层和半导体层，所述掩埋绝缘层位于所述半导体衬底上，所述半导体层位于所述掩埋绝缘层上; 半导体层上的栅极堆叠; 源极区域和漏极区域，其位于半导体层中并且在栅极堆叠的相对侧上; 以及沟道区，其位于所述半导体层中并且被所述源极区和所述漏极区夹持，其中所述MOSFET还包括背栅极，所述后栅极位于所述半导体衬底中，并且在所述半导体衬底的下部具有第一掺杂区域的背栅极和在后栅极的上部中的第二掺杂区域。

2. 发明申请

US20150221769A1 FINFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： FINFET及其制造方法
公开(公告)号：US20150221769A1
公开(公告)日：2015-08-06
申请号：US14419833
申请日：2012-08-24
申请人： Huilong Zhu , Miao Xu
发明人： Huilong Zhu , Miao Xu
IPC分类号： H01L29/78 , H01L21/3065 , H01L29/06 , H01L21/308 , H01L29/66 , H01L29/161
CPC分类号： H01L29/7849 , H01L21/3065 , H01L21/308 , H01L29/0611 , H01L29/0649 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7846 , H01L29/785
摘要： An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括：半导体衬底; 半导体衬底上的应力层; 在所述应力层上的半导体鳍片，所述半导体鳍片具有在其长度方向上延伸的两个侧壁; 半导体鳍片的侧壁上的栅极电介质; 栅极电介质上的栅极导体; 以及半导体鳍片的两端的源极区域和漏极区域，其中应力层在半导体鳍片的下方并且平行地延伸，并且在半导体鳍片的长度方向上对半导体鳍片施加应力。

3. 发明申请

US20130049092A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130049092A1
公开(公告)日：2013-02-28
申请号：US13501518
申请日：2011-11-18
申请人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L29/78654 , H01L29/4908 , H01L29/78603 , H01L29/78648 , H01L29/78696
摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.
摘要翻译：本申请公开了一种包括超薄半导体层中的源极区域和漏极区域的半导体器件; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和所述沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极由低Vt材料制成。根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

4. 发明申请

US20060029620A1 Mycobacterium smegmatis vaccine 审中-公开
标题翻译：耻垢分枝杆菌疫苗
公开(公告)号：US20060029620A1
公开(公告)日：2006-02-09
申请号：US10913626
申请日：2004-08-05
申请人： Guozhi Wang , Miao Xu , Baowen Chen , Xiaobing Shen , Cheng Su , Maoxiang Wang , Yuhe Yin , Yujie Ma
发明人： Guozhi Wang , Miao Xu , Baowen Chen , Xiaobing Shen , Cheng Su , Maoxiang Wang , Yuhe Yin , Yujie Ma
IPC分类号： A61K39/04
CPC分类号： A61K39/04 , A61K2039/521
摘要： The present invention is about a mycobacterium smegmatis vaccine, a split product of mycobacterium smegmatis. This vaccine has made good use of the adjuvant function of bacterial cellwall and antigenic specificity of tropina which can stimulate the production of cytokine and consists of many immunologically competent CpG fragments of bacteria DNA. Such vaccine is prepared by treating newly-cultured thalli with a physical quassation technique. This vaccine is capable of enhancing normal immune function against TB, promoting the recovery of normal immune function in TB patients with hypofunction, and depressing the immunological responses in TB patients with hyperfunction. It is especially effective in the prevention and treatment of MTB carriers.
摘要翻译：本发明涉及耻垢分枝杆菌分枝杆菌疫苗，分枝杆菌属的分裂产物。这种疫苗充分利用了细菌细胞壁的辅助功能和抗原特异性，可以刺激细胞因子的产生，并由细菌DNA的许多免疫学能力的CpG片段组成。这种疫苗是通过用物理方法处理新培养的thalli来制备的。该疫苗能够增强结核病的正常免疫功能，促进TB功能低下的正常免疫功能的恢复，抑制TB功能异常的免疫反应。在MTB载体的预防和治疗方面特别有效。

5. 发明授权

US06196242B1 Hanging sun umbrella 失效
标题翻译：挂太阳伞
公开(公告)号：US06196242B1
公开(公告)日：2001-03-06
申请号：US09076474
申请日：1998-05-13
申请人： Zhen Miao Xu
发明人： Zhen Miao Xu
IPC分类号： A45B1100
CPC分类号： A45B23/00 , A45B25/14 , A45B2023/005 , A45B2025/146
摘要： A hanging sun umbrella includes a column; an umbrella frame including a hanging arm; a movable hanging arm holder for movably attaching the hanging arm to the column; a pull arm extending from the column above the hanging arm holder, wherein the hanging arm, the hanging arm holder, and the pull arm provide a cantilevered shape to the umbrella frame; a crank lift provided on the column to move the movable hanging arm holder up and down along the column for opening and closing the umbrella; and an umbrella cloth fitted on the umbrella frame. The umbrella frame, which is attached to the column, includes (a) the hanging arm hingedly attached to the column, (b) a hanging arm bracing hingedly attached to the hanging arm via a tube clamp, (c) six to eight umbrella rods, (d) an umbrella rod bracing hingedly extending from each umbrella rod via a tube clamp, (e) an upper umbrella tray holder hingedly connected to the hanging arm and each umbrella rod, and (f) a lower umbrella tray holder hingedly connected to the hanging arm bracing and each umbrella rod bracing.
摘要翻译：挂太阳伞包括一列; 包括吊臂的伞架; 用于将悬挂臂可移动地附接到柱的可移动悬挂臂保持器; 从所述悬挂臂保持器上方的所述列延伸的拉臂，其中所述悬挂臂，所述悬臂支架和所述拉臂在伞架上提供悬臂形状; 设置在所述塔上的曲柄升降机，用于沿所述塔上下移动所述可动悬臂支架以打开和关闭所述伞; 以及安装在伞架上的伞布。附接到柱的伞形框架包括（a）悬挂臂，铰接地连接到柱上，（b）悬挂臂支撑件，通过管夹铰接地附接到悬挂臂，（c）六至八个伞杆（d）从每个伞杆经由管夹铰接地延伸的伞杆支撑件，（e）铰接地连接到悬挂臂和每个伞杆的上伞托架，以及（f）下伞托架托架，铰链连接到吊臂支撑和每个伞杆支撑。

6. 发明授权

US09633854B2 MOSFET and method for manufacturing the same 有权
公开(公告)号：US09633854B2
公开(公告)日：2017-04-25
申请号：US13379433
申请日：2011-08-02
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66 , H01L29/786 , H01L21/26
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/78648
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate.

7. 发明授权

US08933512B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US08933512B2
公开(公告)日：2015-01-13
申请号：US13208964
申请日：2011-08-12
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/772 , H01L29/786
CPC分类号： H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI wafer, which comprises a bottom semiconductor substrate, a first buried insulating layer on the bottom semiconductor substrate, and a first semiconductor layer on the first buried insulating layer; a source region and a drain region which are formed in a second semiconductor layer over the SOI wafer, wherein there is a second buried insulating layer between the second semiconductor layer and the SOI wafer; a channel region, which is formed in the second semiconductor layer and located between the source region and the drain regions; and a gate stack, which comprises a gate dielectric layer on the second semiconductor layer and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the first semiconductor substrate below the channel region, the backgate having a non-uniform doping profile, and the second buried insulating layer serving as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the polarity of dopants and/or the doping profile in the backgate. Leakage in the semiconductor device can be reduced.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括SOI晶片，其包括底部半导体衬底，底部半导体衬底上的第一掩埋绝缘层和第一掩埋绝缘层上的第一半导体层; 源极区和漏极区，形成在SOI晶片上的第二半导体层中，其中在第二半导体层和SOI晶片之间存在第二掩埋绝缘层; 沟道区，其形成在所述第二半导体层中并且位于所述源极区和所述漏极区之间; 以及栅极堆叠，其包括在所述第二半导体层上的栅极介电层和所述栅极电介质层上的栅极导体，其中所述MOSFET还包括形成在所述沟道区域下方的所述第一半导体衬底的一部分中的后栅极，不均匀的掺杂分布，以及用作背栅的栅介电层的第二掩埋绝缘层。通过改变背栅中的掺杂剂的极性和/或掺杂分布，MOSFET具有可调节的阈值电压。可以减少半导体器件中的泄漏。

8. 发明授权

US09012963B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09012963B2
公开(公告)日：2015-04-21
申请号：US13501518
申请日：2011-11-18
申请人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/66 , H01L29/786 , H01L29/49
CPC分类号： H01L29/78654 , H01L29/4908 , H01L29/78603 , H01L29/78648 , H01L29/78696
摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.
摘要翻译：本申请公开了一种半导体器件，其包括超薄半导体层中的源极区域和漏极区域; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极由低Vt材料制成。根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

9. 发明授权

US08716799B2 MOSFET 有权
公开(公告)号：US08716799B2
公开(公告)日：2014-05-06
申请号：US13376996
申请日：2011-08-01
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/78648 , H01L21/2652
摘要： The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate.
摘要翻译：本申请公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘体层和半导体层，所述埋入绝缘体层设置在所述半导体基板上，并且所述半导体层设置在所述埋入绝缘体层上; 栅极堆叠，其设置在半导体层上; 源极区域和漏极区域，其设置在所述半导体层中并且在所述栅极堆叠的相对侧上; 以及沟道区域，其设置在所述半导体层中并且被所述源极区域和所述漏极区域夹持，其中所述MOSFET还包括设置在所述半导体衬底中的背栅极，并且其中所述后栅极包括第一，第二和第三补偿掺杂第一补偿掺杂区域设置在源极区域和漏极区域下方; 所述第二补偿掺杂区域在远离所述沟道区域并邻接所述第一补偿掺杂区域的方向上延伸; 并且第三补偿掺杂区域设置在沟道区域的下方并与第一补偿掺杂区域相邻。通过改变背栅的掺杂类型，MOSFET可以具有可调的阈值电压，并且可以具有减小的寄生电容和与后栅极相关联的降低的接触电阻。

10. 发明申请

US20130099315A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130099315A1
公开(公告)日：2013-04-25
申请号：US13510461
申请日：2011-11-18
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/66742 , H01L29/78609
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘层和半导体层，所述埋入绝缘层位于所述半导体基板上，半导体层位于掩埋绝缘层上; 半导体层上的栅极堆叠; 源极区域和漏极区域，其位于半导体层中并且在栅极堆叠的相对侧上; 以及沟道区，其位于所述半导体层中并且被所述源极区和所述漏极区夹持，其中所述MOSFET还包括背栅极，所述后栅极位于所述半导体衬底中，并且在所述半导体衬底的下部具有第一掺杂区域的背栅极和在后栅极的上部中的第二掺杂区域。 MOSFET可以通过改变反掺杂区域的掺杂浓度和掺杂浓度来调节阈值电压。

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