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1. 发明授权

US08703617B2 Method for planarizing interlayer dielectric layer 有权
标题翻译：平面化层间电介质层的方法
公开(公告)号：US08703617B2
公开(公告)日：2014-04-22
申请号：US13147044
申请日：2011-02-17
申请人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
IPC分类号： H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/76819 , H01L21/31055 , H01L21/31116
摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.
摘要翻译：本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

2. 发明授权

US08324061B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08324061B2
公开(公告)日：2012-12-04
申请号：US13129419
申请日：2011-02-17
申请人： Huaxiang Yin , Qiuxia Xu , Gaobo Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Gaobo Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/31055 , H01L21/31116 , H01L21/76819 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

3. 发明申请

US20120164838A1 METHOD FOR PLANARIZING INTERLAYER DIELECTRIC LAYER 有权
标题翻译：用于平面化介质层电介质层的方法
公开(公告)号：US20120164838A1
公开(公告)日：2012-06-28
申请号：US13147044
申请日：2011-02-17
申请人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
IPC分类号： H01L21/263
CPC分类号： H01L21/76819 , H01L21/31055 , H01L21/31116
摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.
摘要翻译：本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

4. 发明申请

US20120164808A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120164808A1
公开(公告)日：2012-06-28
申请号：US13129419
申请日：2011-02-17
申请人： Huaxiang Yin , Qiuxia Xu , Gaobo Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Gaobo Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/31055 , H01L21/31116 , H01L21/76819 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

5. 发明授权

US08541296B2 Method of manufacturing dummy gates in gate last process 有权
标题翻译：门最后工序中制造虚拟门的方法
公开(公告)号：US08541296B2
公开(公告)日：2013-09-24
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

6. 发明授权

US08501500B2 Method for monitoring the removal of polysilicon pseudo gates 有权
标题翻译：监测多晶硅伪栅极去除的方法
公开(公告)号：US08501500B2
公开(公告)日：2013-08-06
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

7. 发明申请

US20130059435A1 Method of Manufacturing Dummy Gates in Gate Last Process 有权
标题翻译：闸门最后工序制造虚拟闸门的方法
公开(公告)号：US20130059435A1
公开(公告)日：2013-03-07
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

8. 发明申请

US20120322172A1 METHOD FOR MONITORING THE REMOVAL OF POLYSILICON PSEUDO GATES 有权
标题翻译：用于监测多晶硅PSEUDO门的拆卸方法
公开(公告)号：US20120322172A1
公开(公告)日：2012-12-20
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

9. 发明授权

US08252689B2 Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process 有权
标题翻译：化学机械平面化方法及其制造方法
公开(公告)号：US08252689B2
公开(公告)日：2012-08-28
申请号：US13142736
申请日：2011-04-12
申请人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
发明人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/31155 , H01L29/66545 , H01L29/66606 , H01L29/78
摘要： The present invention provides a chemical-mechanical planarization method. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP.
摘要翻译：本发明提供了一种化学机械平面化方法。化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率由CMP。

10. 发明申请

US20120135589A1 CHEMICAL-MECHANICAL PLANARIZATION METHOD AND METHOD FOR FABRICATING METAL GATE IN GATE-LAST PROCESS 有权
标题翻译：化学机械平面化方法和方法，用于在门过程中制造金属门
公开(公告)号：US20120135589A1
公开(公告)日：2012-05-31
申请号：US13142736
申请日：2011-04-12
申请人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
发明人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
IPC分类号： H01L21/306 , H01L21/304 , H01L21/28
CPC分类号： H01L21/31053 , H01L21/31155 , H01L29/66545 , H01L29/66606 , H01L29/78
摘要： The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, thereby improving the within-die uniformity of the process, consequently, there will not be excess metal in the insulating layer between gates, thereby preventing device short circuit risk induced by POP CMP process.
摘要翻译：本发明提供一种化学机械平面化方法及其制造方法。化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率通过CMP，从而提高了工艺的管芯内均匀性，因此在栅极之间的绝缘层中不会有过多的金属，从而防止POP CMP工艺引起的器件短路风险。

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