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1. 发明专利

JP2013172019A Substrate processing apparatus and substrate processing method 有权
标题翻译：基板处理装置和基板处理方法
公开(公告)号：JP2013172019A
公开(公告)日：2013-09-02
申请号：JP2012035365
申请日：2012-02-21
申请人： Ebara Corp , 株式会社荏原製作所 , Toshiba Corp , 株式会社東芝
发明人： ISHII YU , KAWASAKI HIROYUKI , NAGAOKA KENICHI , ITO KENYA , KODERA MASAKO , TOMITA HIROSHI , NISHIOKA TAKESHI
IPC分类号： H01L21/304 , B08B1/04
CPC分类号： B08B1/001 , H01L21/67046 , H01L21/67051 , H01L21/68728
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing apparatus which efficiently removes foreign objects adhering to a front surface and/or a rear surface of a substrate achieving a high removal ratio.SOLUTION: A substrate processing apparatus includes: a scrubber 50 causing a scrub member 61 to slidably contact with a first surface of a substrate W to perform surface treatment of the substrate W; a static pressure support mechanism 90 supporting a second surface of the substrate W, which is the opposite side of the first surface, using fluid pressure in a non-contact manner; a cleaning part 27 cleaning the substrate W on which the surface treatment is performed by the scrubber 50; and a dry part 100 drying the cleaned substrate W. The scrubber 50 rotates the scrub member 61 around its shaft center and causes the scrub member 61 to slidably contact with the first surface of the substrate W.
摘要翻译：要解决的问题：提供一种能够有效地去除附着在基板的前表面和/或后表面上的异物的基板处理装置，实现高的去除率。解决方案：基板处理装置包括：洗涤器50，其产生擦洗构件61与衬底W的第一表面滑动接触以对衬底W进行表面处理; 以非接触方式使用流体压力支撑作为第一表面的相对侧的基板W的第二表面的静压支撑机构90; 清洁部分27，清洁由洗涤器50执行表面处理的基板W; 和干燥部分100干燥清洁的基底W.洗涤器50围绕其轴心旋转擦洗部件61，并使擦洗部件61与基板W的第一表面滑动接触。

2. 发明专利

JP2011177842A Polishing apparatus and method 审中-公开
标题翻译：抛光装置和方法
公开(公告)号：JP2011177842A
公开(公告)日：2011-09-15
申请号：JP2010044846
申请日：2010-03-02
申请人： Ebara Corp , Toshiba Corp , 株式会社東芝 , 株式会社荏原製作所
发明人： NAKANISHI MASAYUKI , TOGAWA TETSUJI , ITO KENYA , SEKI MASAYA , IWADE KENJI , KUBOTA TAKEO , NISHIOKA TAKESHI
IPC分类号： B24B21/00 , B24B9/00 , B24B21/18 , B24B53/10
CPC分类号： B24B1/00 , B24B55/00
摘要： PROBLEM TO BE SOLVED: To prevent abrasive particles from falling from a polishing tape as much as possible during polishing; and to prevent the fallen abrasive particles from entering an element forming area or the like in a center of a substrate even if the abrasive particles are fallen from the polishing tape during polishing a surface peripheral part of the substrate. SOLUTION: A polishing apparatus includes: a polishing head 12 that polishes a surface of the substrate W by pressing a surface of the polishing tape 20 to a surface of the substrate W while running the polishing tape 20, which has the abrasive particles fixed on the surface thereof, in one direction; and a conditioning apparatus (cleaning apparatus) 30 that is arranged at an upstream side of the polishing head 12 along the running direction of the polishing tape 20 and that conditions the surface in advance for preventing the abrasive particles from falling during polishing the surface of the polishing tape 20. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止磨料颗粒在抛光过程中尽可能多地从研磨带落下; 并且即使在抛光衬底的表面周边部分期间研磨颗粒从研磨带中掉落时，也可防止掉落的磨料颗粒进入衬底中心的元件形成区域等。解决方案：抛光装置包括：抛光头12，其抛光基材W的表面，通过将研磨带20的表面压在基板W的表面上，同时运行具有磨料颗粒的研磨带20 在一个方向上固定在其表面上; 以及沿研磨带20的行进方向配置在研磨头12的上游侧的调理装置（清洗装置）30，并且预先调整表面，以防止研磨颗粒在抛光过程中的表面抛光抛光胶带20.版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2017118146A スクラバー有权
公开(公告)号：JP2017118146A
公开(公告)日：2017-06-29
申请号：JP2017051113
申请日：2017-03-16
申请人：株式会社荏原製作所 , Ebara Corp , 株式会社東芝 , Toshiba Corp
发明人： ISHII YU , KAWASAKI HIROYUKI , NAGAOKA KENICHI , ITO KENYA , KODERA MASAKO , TOMITA HIROSHI , NISHIOKA TAKESHI
IPC分类号： H01L21/304 , B08B1/04 , B24B21/06
摘要：【課題】基板の表面および/または裏面に付着した異物を高い除去率で効率よく除去することができるスクラバーを提供する。【解決手段】スクラバー50は、その内部に基板Wの第1の面に摺接させて第1の面の表面処理を行うテープ状の複数のスクラブ部材61と、複数のスクラブ部材61をそれぞれ繰り出す複数のテープ繰り出しリール64と、複数のスクラブ部材61をそれぞれ巻き取る複数のテープ巻き取りリール65と、複数のテープ巻き取りリール65がそれぞれ連結された複数のテープ巻き取り軸67とを備え、スクラバー50は、スクラバー50の軸心周りに複数のスクラブ部材61を回転させながら複数のスクラブ部材61を基板Wの第1の面に摺接させる。【選択図】図8

4. 发明专利

JP2010245148A Chemical mechanical polishing method, semiconductor device using the same, and kit for preparing aqueous dispersion for chemical mechanical polishing 有权
标题翻译：化学机械抛光方法，使用其的半导体器件和用于制备用于化学机械抛光的水性分散体的工具包
公开(公告)号：JP2010245148A
公开(公告)日：2010-10-28
申请号：JP2009089889
申请日：2009-04-02
申请人： Jsr Corp , Jsr株式会社 , Toshiba Corp , 株式会社東芝
发明人： TAKEMURA AKIHIRO , ABE TAICHI , SHIDA HIROTAKA , HIRASAWA SHINICHI , IWADE KENJI , NISHIOKA TAKESHI
IPC分类号： H01L21/304 , B24B37/00 , C09K3/14
摘要： PROBLEM TO BE SOLVED: To provide a chemical mechanical polishing method for evenly polishing a processing object with a wiring layer containing tungsten at a high speed. SOLUTION: The chemical mechanical polishing method includes: a first polishing process for chemically and mechanically polishing only a tungsten film by using a first aqueous dispersion for chemical mechanical polishing; a second polishing process for chemically and mechanically polishing the tungsten film, barrier metal film; and silicon oxide film simultaneously by using a second aqueous dispersion for chemical mechanical polishing. The first and second aqueous dispersions for chemical mechanical polishing contain at least (A) cationic water-soluble polymer, (B) an iron (III) compound, and (C) colloidal silica. A content ratio (M A1 /M A2 ) of a content (M A1 ) [mass%] of the component (A) in the first aqueous dispersion for chemical mechanical polishing to a content (M A2 ) [mass%] of the component (A) in the second aqueous dispersion for chemical mechanical polishing is 0.004-0.3. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于以高速对包含钨的布线层均匀抛光处理对象的化学机械抛光方法。解决方案：化学机械抛光方法包括：通过使用用于化学机械抛光的第一水分散体来化学和机械抛光钨膜的第一抛光工艺; 用于化学和机械抛光钨膜，阻挡金属膜的第二抛光工艺; 和氧化硅膜同时使用第二水分散体用于化学机械抛光。用于化学机械抛光的第一和第二水性分散体至少含有（A）阳离子水溶性聚合物，（B）铁（III）化合物和（C）胶体二氧化硅。组分（A）的含量（M A1 ）[质量％]的含量比（M A1 / M SB> A2 ）用于化学机械抛光的第一水分散体用于化学机械抛光的第二水性分散体中组分（A）的含量（M SB> A2 ）[质量％]为0.004-0.3。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2007258510A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007258510A
公开(公告)日：2007-10-04
申请号：JP2006082042
申请日：2006-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUI YUKITERU , HIRASAWA SHINICHI , SHIGETA ATSUSHI , MIYANO KIYOTAKA , NISHIOKA TAKESHI , YANO HIROYUKI
IPC分类号： H01L21/8247 , B24B37/00 , H01L21/28 , H01L21/304 , H01L21/3205 , H01L21/321 , H01L21/336 , H01L21/76 , H01L21/768 , H01L23/52 , H01L23/532 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11543 , C09G1/02 , H01L21/3212 , H01L21/7684 , H01L27/11526
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device containing a laminated gate structure having improved device characteristics with a high yield. SOLUTION: The method for manufacturing a semiconductor device comprises: a process for forming a gate insulating film, a first silicon film, and a mask film on a semiconductor substrate; a process for forming a plurality of grooves on the first silicon film and the mask film while reaching the semiconductor substrate; a process for embedding a silicon oxide film into the plurality of grooves; a process for exposing the first silicon film between the embedded silicon oxide films by removing the mask film; a process for selectively growing the second silicon film on the first silicon film; a process for flattening the second silicon film by using alkali slurry that contains polishing particles and a cationic surface-active agent and has a pH13 or smaller for obtaining a floating gate electrode film made of the first and second silicon films; and a process for successively forming an insulating film between electrodes and a control gate electrode film on the floating gate electrode film and the silicon oxide film. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造包含具有高产率的改进的器件特性的层叠栅极结构的半导体器件的方法。解决方案：半导体器件的制造方法包括：在半导体衬底上形成栅极绝缘膜，第一硅膜和掩模膜的工艺; 在到达半导体衬底的同时在第一硅膜和掩模膜上形成多个沟槽的工艺; 将氧化硅膜嵌入到所述多个槽中的工序; 通过去除掩模膜将第一硅膜暴露于嵌入的氧化硅膜之间的工艺; 用于在第一硅膜上选择性地生长第二硅膜的工艺; 通过使用含有研磨粒子和阳离子性表面活性剂的碱性浆液使第二硅膜平坦化并具有pH13以下的工序，得到由第一和第二硅膜构成的浮栅电极膜; 以及在浮栅电极膜和氧化硅膜之间在电极之间连续形成绝缘膜和控制栅极电极膜的工艺。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007115980A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007115980A
公开(公告)日：2007-05-10
申请号：JP2005307304
申请日：2005-10-21
申请人： Toshiba Corp , 株式会社東芝
发明人： MORITA TOSHIYUKI , NISHIOKA TAKESHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： H01L21/2885 , H01L21/76838 , H01L21/76877 , H01L23/522 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has been improved both in initial electrical characteristics and in stress migration reliability. SOLUTION: The semiconductor device comprises a semiconductor substrate; an interlayer dielectric 2 formed on the semiconductor substrate; an interlayer dielectric formed on the interlayer dielectric 2; a wiring 3 disposed in the interlayer dielectric 2 and having a plug connection portion 3a; a via plug formed in the interlayer dielectric and connected to the plug connection portion 3a; a plurality of first dummy wirings 4 formed in the interlayer dielectric 2 near the plug connection portion 3a; and a plurality of second dummy wirings 5 that are formed in the interlayer dielectric 2 near the portion of the wiring 3 excluding the plug connection portion 3a, and that each has at least any one of a width smaller than that of the first dummy wiring 4 and a pattern coverage per unit larger than that of the dummy wiring 4. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供在初始电特性和应力迁移可靠性方面都得到改善的半导体器件。半导体器件包括半导体衬底; 形成在半导体衬底上的层间电介质2; 形成在层间电介质2上的层间电介质; 布置在层间电介质2中并具有插头连接部分3a的布线3; 形成在层间电介质中并连接到插头连接部分3a的通孔塞; 在插塞连接部分3a附近形成在层间电介质2中的多个第一虚拟布线4; 以及多个第二虚拟布线5，其形成在除了插头连接部3a以外的布线3的部分附近的层间电介质2中，并且各自具有比第一伪布线4的宽度小的至少任一个并且每单位的图案覆盖率大于虚拟布线4的版图覆盖率。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2005229086A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005229086A
公开(公告)日：2005-08-25
申请号：JP2004195731
申请日：2004-07-01
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA NORIAKI , NAKAMURA NAOFUMI , ITO SACHIYO , HASUNUMA MASAHIKO , NISHIOKA TAKESHI
IPC分类号： H01L23/52 , H01L21/00 , H01L21/3205 , H01L21/822 , H01L23/00 , H01L23/522 , H01L23/58 , H01L27/04 , H01L27/10 , H01L29/40
CPC分类号： H01L23/564 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent the occurrence of cracks in interlayer insulating films, the delamination of the films, the permeation of moisture or gas into the films. SOLUTION: A semiconductor device has a first insulating layer 211 provided on a semiconductor substrate 1. The first insulating layer includes one layer made of a material having a relative dielectric constant smaller than 3. The first insulating layer includes an integral structure consisting of a plug 213 and wiring 212. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member 56 is formed of an integral structure consisting of a plug and wiring, which extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer, and surrounds one of first to n-th regions (n: a natural number of ≥2) partitioned by a boundary region 55 on a plane. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够防止层间绝缘膜发生裂纹的半导体器件，膜的分层，水分或气体渗透到膜中。解决方案：半导体器件具有设置在半导体衬底1上的第一绝缘层211.第一绝缘层包括由相对介电常数小于3的材料制成的一层。第一绝缘层包括整体结构，其包括插头213和布线212.布线的上表面与第一绝缘层的上表面齐平，插头的下表面与第一绝缘层的下表面齐平。区域保护构件56由从第一绝缘层的上表面延伸到第一绝缘层的下表面的插头和布线构成的一体结构形成，并且包围第一至第n区域中的一个 n：由平面上的边界区域55划分的≥2的自然数。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2007318171A Method and device for heat treatment of semiconductor substrate 审中-公开
标题翻译：用于半导体基板的热处理的方法和装置
公开(公告)号：JP2007318171A
公开(公告)日：2007-12-06
申请号：JP2007204537
申请日：2007-08-06
申请人： Toshiba Corp , 株式会社東芝
发明人： TATSUTA SHINICHI , NISHIOKA TAKESHI , HIRONO MASATOSHI , SUGURO KYOICHI , ITO TAKAYUKI
IPC分类号： H01L21/26 , H01L21/265
摘要： PROBLEM TO BE SOLVED: To provide a method and device for heat treatment which sufficiently activate an impurity diffusion layer without causing temperature irregularity or hot spots on a semiconductor substrate, and give the impurity diffusion layer a desired profile. SOLUTION: The method performs the heat treatment of the semiconductor substrate 205 using a light source 100 to activate an impurity injected into the semiconductor substrate 205. The method includes a light-absorbing film formation step of forming a light-absorbing film 250 on the surface of the semiconductor substrate 205, which light-absorbing film 250 is made of a material having a refraction factor n-ik with a real part n of 0.5 to 2.2 and an imaginary part k of 1.0 or less and absorbs light energy from the light source 100 to turn the light energy into heat energy, and a heat treatment step of emitting light energy from the light source 100 onto the light-absorbing film 250 to activate the impurity. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种热处理方法和装置，其充分激活杂质扩散层而不引起半导体衬底上的温度不均匀或热点，并且给予杂质扩散层所需的特性。解决方案：该方法使用光源100对半导体衬底205进行热处理，以激活注入到半导体衬底205中的杂质。该方法包括形成光吸收膜250的光吸收膜形成步骤在半导体基板205的表面上，该光吸收膜250由具有折射系数n-ik的材料制成，实部n为0.5至2.2，虚部k为1.0或更小，并且吸收来自光源100将光能转换成热能;以及热光处理步骤，其将光能从光源100发射到光吸收膜250上以激活杂质。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006156998A Pattern generation method, manufacturing method for semiconductor device, semiconductor device, and program 有权
标题翻译：图形生成方法，半导体器件的制造方法，半导体器件和程序
公开(公告)号：JP2006156998A
公开(公告)日：2006-06-15
申请号：JP2005321571
申请日：2005-11-04
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HATANO SHOSUKE , NISHIOKA TAKESHI , FUJIMAKI TAKESHI , OKAZAKI MOTOYA , WADA JUNICHI , KANEKO HISAFUMI , AZUMA KAZUYUKI , YOSHIDA KENJI , MATSUNAGA NORIAKI
IPC分类号： H01L21/3205 , G06F17/50 , H01L21/82 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a pattern generation method capable of increasing the pattern coverage rate of the peripheral region of an isolated pattern.
SOLUTION: After a wiring pattern arranged on an interlayer dielectric film and the wiring layout and hole layout of a hole pattern embedded in the interlayer dielectric film are obtained, the hole pattern is extracted, which is connected with the wiring pattern from the hole layout in a pattern processing region where the wiring pattern is arranged in the same wiring layer. A primary processing region is extracted so that the hole pattern may be included, and the pattern coverage rate of the wiring pattern included in the primary processing region is computed. After that, additional patterns are generated in the primary processing region based on the pattern coverage rate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够提高隔离图案的周边区域的图案覆盖率的图案生成方法。解决方案：在布置在层间电介质膜上的布线图案和嵌入在层间电介质膜中的孔图案的布线布局和孔布局之后，提取孔图案，其与布线图案相连布线图案布置在同一布线层中的图案处理区域中的孔布局。提取主处理区域，使得可以包括空穴图案，并且计算包括在主处理区域中的布线图案的图案覆盖率。之后，基于模式覆盖率，在主处理区域中产生附加模式。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2009146998A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009146998A
公开(公告)日：2009-07-02
申请号：JP2007320962
申请日：2007-12-12
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUI YUKITERU , SHIGETA ATSUSHI , TATEYAMA YOSHIKUNI , NISHIOKA TAKESHI , YANO HIROYUKI
IPC分类号： H01L21/3205 , B24B37/00 , H01L21/304 , H01L21/321 , H01L21/768
CPC分类号： H01L21/76811 , C09G1/02 , H01L21/31058 , H01L21/31144 , H01L21/312 , H01L21/76813 , H01L21/76835
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device in which an organic film is made flat while defects are reduced and dual damascene wiring can be formed in high yield. SOLUTION: The method for manufacturing a semiconductor device includes: a process for forming a coated film by applying a solution containing a solvent and an organic component onto an insulating film which is provided above a semiconductor substrate 20 and has a recessed part; a process for obtaining an organic film precursor by baking the coated film at a first temperature where cross-linking of the organic component is not completed; a process for making a surface of the organic film precursor flat by polishing the organic film precursor using a first slurry containing first resin particles and a water-soluble polymer; and a process in which the organic film precursor whose surface is made flat, is polished using a second slurry containing second resin particles and a water-soluble polymer and the organic film precursor is left in the recessed part, thereby exposing the insulating film. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其中有机膜被制成平坦的同时缺陷减少并且可以以高产率形成双镶嵌布线。解决方案：半导体器件的制造方法包括：通过将含有溶剂和有机成分的溶液涂布在设置在半导体基板20的上方并具有凹部的绝缘膜上形成涂膜的工序; 通过在没有完成有机成分的交联的第一温度下烘烤涂膜来获得有机膜前体的方法; 通过使用含有第一树脂颗粒和水溶性聚合物的第一浆料研磨有机膜前体来使有机膜前体的表面平坦化的方法; 并且使用含有第二树脂颗粒和水溶性聚合物的第二浆料将有机膜前体的表面平坦化的方法抛光，并且将有机膜前体留在凹部中，由此露出绝缘膜。版权所有（C）2009，JPO＆INPIT

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