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1. 发明授权

US07563704B2 Method of forming an interconnect including a dielectric cap having a tensile stress 有权
标题翻译：形成包括具有拉伸应力的电介质盖的互连的方法
公开(公告)号：US07563704B2
公开(公告)日：2009-07-21
申请号：US11162666
申请日：2005-09-19
申请人： Chih-Chao Yang , Kaushik Chanda , Lawrence A. Clevenger , Yun-Yu Wang , Daewon Yang
发明人： Chih-Chao Yang , Kaushik Chanda , Lawrence A. Clevenger , Yun-Yu Wang , Daewon Yang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
摘要翻译：提供了互连结构及其制造方法。互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

2. 发明申请

US20070063348A1 METHOD AND STRUCTURE OF FORMING AN INTERCONNECT INCLUDING A DIELECTRIC CAP HAVING A TENSILE STRESS 有权
标题翻译：形成互连的方法和结构，包括具有拉伸应力的电介质盖
公开(公告)号：US20070063348A1
公开(公告)日：2007-03-22
申请号：US11162666
申请日：2005-09-19
申请人： Chih-Chao Yang , Kaushik Chanda , Lawrence Clevenger , Yun-Yu Wang , Daewon Yang
发明人： Chih-Chao Yang , Kaushik Chanda , Lawrence Clevenger , Yun-Yu Wang , Daewon Yang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
摘要翻译：提供了互连结构及其制造方法。互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

3. 发明授权

US07494915B2 Back end interconnect with a shaped interface 失效
标题翻译：后端互连与成形接口
公开(公告)号：US07494915B2
公开(公告)日：2009-02-24
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

4. 发明授权

US07122462B2 Back end interconnect with a shaped interface 有权
公开(公告)号：US07122462B2
公开(公告)日：2006-10-17
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

5. 发明授权

US07102232B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

6. 发明授权

US06921978B2 Method to generate porous organic dielectric 失效
公开(公告)号：US06921978B2
公开(公告)日：2005-07-26
申请号：US10249799
申请日：2003-05-08
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

7. 发明申请

US20080254643A1 STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER 有权
标题翻译：结构提高顶级CVD低K电介质和介电吸收层之间的粘合力
公开(公告)号：US20080254643A1
公开(公告)日：2008-10-16
申请号：US12143917
申请日：2008-06-23
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

8. 发明授权

US07402532B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07402532B2
公开(公告)日：2008-07-22
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

9. 发明授权

US07820559B2 Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer 有权
标题翻译：用于改善顶部CVD低K电介质和介电顶盖层之间粘合的结构
公开(公告)号：US07820559B2
公开(公告)日：2010-10-26
申请号：US12143917
申请日：2008-06-23
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/31 , H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘附过渡层包括下部含SiO x或SiON的区域和上部C分级区域。还提供了形成这种结构，特别是粘附过渡层的方法。

10. 发明授权

US07101784B2 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US07101784B2
公开(公告)日：2006-09-05
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

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