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1. 发明授权

US07101784B2 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US07101784B2
公开(公告)日：2006-09-05
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

2. 发明授权

US07521345B2 High-temperature stable gate structure with metallic electrode 失效
标题翻译：具有金属电极的高温稳定栅极结构
公开(公告)号：US07521345B2
公开(公告)日：2009-04-21
申请号：US11782351
申请日：2007-07-24
申请人： Dae-Gyu Park , Oleg G. Gluschenkov , Michael A. Gribelyuk , Kwong H. Wong
发明人： Dae-Gyu Park , Oleg G. Gluschenkov , Michael A. Gribelyuk , Kwong H. Wong
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.
摘要翻译：本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

3. 发明授权

US07012499B2 Method of fabrication of thin film resistor with 0 TCR 有权
标题翻译：具有0 TCR的薄膜电阻器的制造方法
公开(公告)号：US07012499B2
公开(公告)日：2006-03-14
申请号：US10250075
申请日：2003-06-02
申请人： Jeffrey R. Amadon , Anil K. Chinthakindi , Kenneth J. Stein , Kwong H. Wong
发明人： Jeffrey R. Amadon , Anil K. Chinthakindi , Kenneth J. Stein , Kwong H. Wong
IPC分类号： H01C7/06
CPC分类号： H01C7/06 , H01C7/006
摘要： A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).
摘要翻译：提供具有基本为零TCR的薄膜电阻器及其制造方法。薄膜电阻器包括彼此位于的至少两个电阻材料。每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。

4. 发明授权

US06921978B2 Method to generate porous organic dielectric 失效
公开(公告)号：US06921978B2
公开(公告)日：2005-07-26
申请号：US10249799
申请日：2003-05-08
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

5. 发明授权

US06436760B1 Method for reducing surface oxide in polysilicon processing 失效
标题翻译：多晶硅加工中减少表面氧化物的方法
公开(公告)号：US06436760B1
公开(公告)日：2002-08-20
申请号：US09838418
申请日：2001-04-19
申请人： Kwong H. Wong , Ashima B. Chakravarti , Satya N. Chakravarti , Subramanian S. Iyer
发明人： Kwong H. Wong , Ashima B. Chakravarti , Satya N. Chakravarti , Subramanian S. Iyer
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L21/32132
摘要： A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e.g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.
摘要翻译：用于从多晶硅去除表面氧化物的方法包括在随后的多晶硅沉积步骤之前在多晶硅上沉积非常薄的锗层（例如，厚度为单层），然后在真空中加热锗覆盖的多晶硅以升华（除去）挥发性氧化锗。该方法适用于沟槽电容器的形成，其在电极形成中使用掺杂的非晶硅或掺杂的非晶SiGe材料。

6. 发明授权

US06960831B2 Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad 失效
标题翻译：除了铜布线和铝接合垫之间的阻挡层之外，还具有复合层
公开(公告)号：US06960831B2
公开(公告)日：2005-11-01
申请号：US10605369
申请日：2003-09-25
申请人： Lloyd G. Burrell , Kwong H. Wong , Adreanne A. Kelly , Samuel R. McKnight
发明人： Lloyd G. Burrell , Kwong H. Wong , Adreanne A. Kelly , Samuel R. McKnight
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53223 , H01L24/45 , H01L2224/04042 , H01L2224/05073 , H01L2224/05083 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2924/00011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01327 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, and a method of fabricating the device, having a copper wiring level and an aluminum bond pad above the copper wiring level. In addition to a barrier layer which is normally present to protect the copper wiring level, there is a composite layer between the aluminum bond pad and the barrier layer to make the aluminum bond pad more robust so as to withstand the forces of bonding and probing. The composite layer is a sandwich of a refractory metal and a refractory metal nitride.
摘要翻译：一种半导体器件，以及一种制造该器件的方法，在铜布线层上方具有铜布线层和铝接合焊盘。除了通常存在以保护铜布线水平的阻挡层之外，在铝接合焊盘和阻挡层之间存在复合层，以使铝接合焊盘更坚固，以便承受粘结和探测的力。复合层是难熔金属和难熔金属氮化物的夹层物。

7. 发明授权

US06921711B2 Method for forming metal replacement gate of high performance 有权
标题翻译：形成高性能金属替代门的方法
公开(公告)号：US06921711B2
公开(公告)日：2005-07-26
申请号：US10605106
申请日：2003-09-09
申请人： Cyril Cabral, Jr. , Paul C. Jamison , Victor Ku , Ying Li , Vijay Narayanan , An L Steegen , Yun-Yu Wang , Kwong H. Wong
发明人： Cyril Cabral, Jr. , Paul C. Jamison , Victor Ku , Ying Li , Vijay Narayanan , An L Steegen , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/443
CPC分类号： H01L29/66545 , H01L21/28079 , H01L29/4958
摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.
摘要翻译：提供了一种用于高性能器件的金属替换栅极的结构和方法。首先在设置在半导体衬底上的蚀刻停止层上形成牺牲栅极结构。在牺牲栅极结构的侧壁上设置一对间隔物。然后去除牺牲栅极结构，形成开口。随后，在间隔件之间的开口中形成包括诸如钨的第一金属层的金属栅，诸如氮化钛的扩散阻挡层和诸如钨的第二金属层。

8. 发明授权

US06890810B2 Method of fabrication of thin film resistor with zero TCR 有权
标题翻译：具有零TCR的薄膜电阻器的制造方法
公开(公告)号：US06890810B2
公开(公告)日：2005-05-10
申请号：US10727946
申请日：2003-12-04
申请人： Jeffrey R. Amadon , Anil K. Chinthakindi , Kenneth J. Stein , Kwong H. Wong
发明人： Jeffrey R. Amadon , Anil K. Chinthakindi , Kenneth J. Stein , Kwong H. Wong
IPC分类号： H01C7/00 , H01C7/06 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01C7/06 , H01C7/006
摘要： A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).
摘要翻译：提供具有基本为零TCR的薄膜电阻器及其制造方法。薄膜电阻器包括彼此位于的至少两个电阻材料。每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。

9. 发明授权

US06723600B2 Method for making a metal-insulator-metal capacitor using plate-through mask techniques 有权
标题翻译：使用平板通孔技术制造金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US06723600B2
公开(公告)日：2004-04-20
申请号：US09837805
申请日：2001-04-18
申请人： Kwong H. Wong , Xian J. Ning
发明人： Kwong H. Wong , Xian J. Ning
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/76838 , H01L28/75
摘要： A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric. The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, reduced sheet resistance and surface roughness is achieved, both of which enhance the performance of the capacitor. This performance is further enhanced by forming the capacitor to have a damascene structure. Preferably, at least one conductive interconnect is formed simultaneously with the formation of the capacitor. This is made possible, at least in part, by forming the interconnect using a plate-through mask technique. The interconnect and capacitor are then finished using one and only one planarizing (e.g., CMP) step. The result is to form a capacitor and interconnect structure in far fewer steps than conventionally required, which translates into improved cost and efficiency.
摘要翻译：制造金属 - 绝缘体 - 金属电容结构的方法包括在诸如层间电介质层的支撑结构上沉积铜屏障和种子层，在铜屏障和籽晶层上形成电介质，然后形成电介质上的金属层。铜屏障和种子层形成电容器的底板，并且金属层形成通过电介质与底板分离的上板。通过从铜屏障和种子层形成底板，实现了降低的薄层电阻和表面粗糙度，这两者都增强了电容器的性能。通过形成具有镶嵌结构的电容器来进一步增强该性能。优选地，与电容器的形成同时形成至少一个导电互连。至少部分地通过使用平板穿透技术形成互连来实现这一点。然后使用一个且仅一个平面化（例如CMP）步骤来完成互连和电容器。其结果是形成电容器和互连结构，其步骤远低于常规要求，这转化为成本和效率的提高。

10. 发明授权

US5209817A Selective plating method for forming integral via and wiring layers 失效
标题翻译：形成集成通孔和布线层的选择电镀方法
公开(公告)号：US5209817A
公开(公告)日：1993-05-11
申请号：US748445
申请日：1991-08-22
申请人： Umar M. Ahmad , Daniel G. Berger , Ananda Kumar , Susan J. LaMaire , Keshav B. Prasad , Sudipta K. Ray , Kwong H. Wong
发明人： Umar M. Ahmad , Daniel G. Berger , Ananda Kumar , Susan J. LaMaire , Keshav B. Prasad , Sudipta K. Ray , Kwong H. Wong
IPC分类号： H01L23/498 , H01L23/522 , H05K1/03 , H05K3/00 , H05K3/06 , H05K3/10 , H05K3/18 , H05K3/38 , H05K3/46
CPC分类号： H05K3/4644 , H01L23/49827 , H01L23/5226 , H05K3/4605 , H05K3/465 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H05K1/0306 , H05K2201/0154 , H05K2201/0187 , H05K2203/0597 , H05K2203/072 , H05K3/0023 , H05K3/061 , H05K3/108 , H05K3/184 , H05K3/388 , H05K3/4661
摘要： In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.
摘要翻译：在多层布线结构中，通过诸如铜之类的导电材料的各向同性的沉积，形成导线和通孔，在诸如聚酰亚胺的电介质基底上。在本发明的一个优选实施例中，将铜电镀到沉积在已经形成通孔开口的电介质基底的表面上的薄种子传导层。在种子层上形成在电介质基底表面上的抗蚀剂中的开口形成限定布线和通孔导体特征的图案。电镀铜在各向同性地填充抗蚀剂中的通孔开口和线图案开口，使得当电镀步骤完成时，布线和通孔的上表面是共面的。在添加其后的布线层次时，去除抗蚀剂，并且通孔导体和布线图案被另一个介电层覆盖，该介质层既封装了前一层的导体并用作下一层的基底，其形成方式与前述水平。

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