专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5376844A Programmable logic device with multiplexer-based programmable interconnections 失效
标题翻译：可编程逻辑器件，具有基于复用器的可编程互连
公开(公告)号：US5376844A
公开(公告)日：1994-12-27
申请号：US39944
申请日：1993-03-29
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
摘要翻译：可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。提供其他信号导体用于在组之间传送信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

2. 发明授权

US5485103A Programmable logic array with local and global conductors 失效
标题翻译：具有局部和全局导体的可编程逻辑阵列
公开(公告)号：US5485103A
公开(公告)日：1996-01-16
申请号：US356516
申请日：1994-12-15
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
摘要翻译：可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。提供其他信号导体用于在组之间传送信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

3. 发明授权

US5436575A Programmable logic array integrated circuits 失效
公开(公告)号：US5436575A
公开(公告)日：1995-07-25
申请号：US111693
申请日：1993-08-25
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： G11C8/12 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , G11C8/12 , H03K19/1737 , H03K19/17704
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

4. 发明授权

US5260610A Programmable logic element interconnections for programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路的可编程逻辑元件互连
公开(公告)号：US5260610A
公开(公告)日：1993-11-09
申请号：US754017
申请日：1991-09-03
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

5. 发明授权

US5260611A Programmable logic array having local and long distance conductors 失效
标题翻译：具有本地和长距离导体的可编程逻辑阵列
公开(公告)号：US5260611A
公开(公告)日：1993-11-09
申请号：US880942
申请日：1992-05-08
申请人： Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
发明人： Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
IPC分类号： H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/1774 , H03K19/17792
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.
摘要翻译：可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的网络。提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。

6. 发明授权

US06759870B2 Programmable logic array integrated circuits 有权
公开(公告)号：US06759870B2
公开(公告)日：2004-07-06
申请号：US10372373
申请日：2003-02-20
申请人： Richard G. Cliff , Bahram Ahanin , Craig Schilling Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
发明人： Richard G. Cliff , Bahram Ahanin , Craig Schilling Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , G01R31/318516 , G11C8/12 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17792
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

7. 发明授权

US5850152A Programmable logic array integrated circuit devices 失效
公开(公告)号：US5850152A
公开(公告)日：1998-12-15
申请号：US834998
申请日：1997-04-07
申请人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

8. 发明授权

US5850151A Programmable logic array intergrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US5850151A
公开(公告)日：1998-12-15
申请号：US834996
申请日：1997-04-07
申请人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

9. 发明授权

US06294928B1 Programmable logic device with highly routable interconnect 失效
标题翻译：具有高度可路由互连的可编程逻辑器件
公开(公告)号：US06294928B1
公开(公告)日：2001-09-25
申请号：US08838398
申请日：1997-04-03
申请人： Craig S. Lytle , Kerry S. Veenstra , Francis B. Heile
发明人： Craig S. Lytle , Kerry S. Veenstra , Francis B. Heile
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17728
摘要： A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-200) comprises an input multiplexer region (A-504), logic elements (A-300), input-output pins (A-516), and output multiplexer region (A-508). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-240) that perform desired logic functions and routing functions. The logic elements (B-240) are arranged in larger logic blocks known as logic array blocks (B-230) that have local interconnection systems. The logic array blocks (B-230) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.
摘要翻译：具有高可路由可编程互连结构的可编程逻辑器件架构。逻辑阵列块（LAB），可编程互连结构和其他逻辑元件的布置形成了Clos网络。在满足特定约束之后，保证架构的路由。当中间阶段没有扇出的时候，这个架构是可行的。 AAB（A-200）包括输入多路复用器区域（A-504），逻辑元件（A-300），输入输出引脚（A-516）和输出多路复用器区域（A-508）。此外，逻辑设备和操作逻辑设备的方法。该设备包括执行所需逻辑功能和路由功能的逻辑元件（B-240）。逻辑元件（B-240）被布置在具有本地互连系统的被称为逻辑阵列块（B-230）的较大逻辑块中。逻辑阵列块（B-230）被配置为提供全局互连。该配置提供了一个Clos网络，从而信号可以从任何输入路由到任何输出而不阻塞。

10. 发明授权

US06815981B2 Programmable logic array integrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US06815981B2
公开(公告)日：2004-11-09
申请号：US10361477
申请日：2003-02-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式