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1. 发明授权

US09269770B2 Integrated circuit system with double doped drain transistor 有权
标题翻译：具有双掺杂漏极晶体管的集成电路系统
公开(公告)号：US09269770B2
公开(公告)日：2016-02-23
申请号：US11683655
申请日：2007-03-08
申请人： Yisuo Li , Gang Chen , Francis Benistant , Purakh Raj Verma , Hong Yang , Shao-fu Sanford Chu
发明人： Yisuo Li , Gang Chen , Francis Benistant , Purakh Raj Verma , Hong Yang , Shao-fu Sanford Chu
IPC分类号： H01L29/66 , H01L29/08 , H01L29/78 , H01L29/739
CPC分类号： H01L29/0847 , H01L29/0843 , H01L29/6659 , H01L29/66681 , H01L29/7393 , H01L29/7816 , H01L29/7833
摘要： An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.
摘要翻译：集成电路系统包括：衬底，在衬底上形成栅极，形成具有第一反扩散区域和源极扩散区域的第一漂移区域，邻近栅极第一侧的衬底中的第一漂移区域，以及形成第二漂移区域，具有第二反扩散区域和漏扩散区域，所述衬底中的所述第二漂移区域邻近所述栅极的与所述栅极的第一侧相对的第二侧。

2. 发明授权

US08536016B2 Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
标题翻译：具有分层电容器的集成电路系统及其制造方法
公开(公告)号：US08536016B2
公开(公告)日：2013-09-17
申请号：US13236295
申请日：2011-09-19
申请人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
发明人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
IPC分类号： H01L21/20
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

3. 发明授权

US08138051B2 Integrated circuit system with high voltage transistor and method of manufacture thereof 有权
标题翻译：具有高压晶体管的集成电路系统及其制造方法
公开(公告)号：US08138051B2
公开(公告)日：2012-03-20
申请号：US12488451
申请日：2009-06-19
申请人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
发明人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
IPC分类号： H01L21/336 , H01L29/94 , H01L29/76 , H01L31/119 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/1041 , H01L29/4238
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.
摘要翻译：一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。

4. 发明授权

US06709918B1 Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology 有权
标题翻译：用于铜后端（BEOL）技术的金属绝缘体金属（MIM）电容器和金属电阻器的制造方法
公开(公告)号：US06709918B1
公开(公告)日：2004-03-23
申请号：US10307674
申请日：2002-12-02
申请人： Chit Hwei Ng , Jian Xun Li , Kok Wai Chew , Tjin Tjin Tjoa , Chaw Sing Ho , Shao Fu Sanford Chu
发明人： Chit Hwei Ng , Jian Xun Li , Kok Wai Chew , Tjin Tjin Tjoa , Chaw Sing Ho , Shao Fu Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L28/20 , H01L23/5223 , H01L23/5228 , H01L28/40 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si3N4 or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.
摘要翻译：实现了一种在金铜绝缘体金属（MIM）电容器和金属电阻器Cu铜镶嵌后端工艺中的制造方法。该方法使用双镶嵌工艺形成Cu电容器底部金属板。沉积Si 3 N 4或SiC以在Cu底板上形成电容器电介质层。具有上蚀刻停止层的金属层被沉积并图案化以形成电容器顶板和金属电阻器。图案化终止在电容器电介质层中以防止Cu颗粒污染。沉积绝缘层，并且使用上蚀刻停止层将电容器顶板和金属电阻器的通孔蚀刻以防止过蚀刻和损坏。该方法提供了仅使用一种附加光致抗蚀剂掩模的MIM电容器，同时提高了工艺产量。

5. 发明授权

US06489191B2 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06489191B2
公开(公告)日：2002-12-03
申请号：US10140571
申请日：2002-05-08
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准的CMOS晶体管栅极的方法。通道植入。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。通过第一通道植入物开口注入杂质离子以形成第一阈值调整区域和第一抗穿透区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

6. 发明授权

US08021954B2 Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
标题翻译：具有层状电容器的集成电路系统及其制造方法
公开(公告)号：US08021954B2
公开(公告)日：2011-09-20
申请号：US12471007
申请日：2009-05-22
申请人： Shao-fu Sanford Chu , Shaoqing Zhang , Johnny Kok Wai Chew , Chit Hwei Ng
发明人： Shao-fu Sanford Chu , Shaoqing Zhang , Johnny Kok Wai Chew , Chit Hwei Ng
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且将所述第一组金属层与所述第二组金属层互连以形成电容器。

7. 发明授权

US07721414B2 Method of manufacturing 3-D spiral stacked inductor on semiconductor material 有权
标题翻译：在半导体材料上制造三维螺旋堆叠电感器的方法
公开(公告)号：US07721414B2
公开(公告)日：2010-05-25
申请号：US10962007
申请日：2004-10-08
申请人： Choon-Beng Sia , Kiat Seng Yeo , Shao-fu Sanford Chu , Cheng Yeow Ng , Kok Wai Chew , Wang Ling Goh
发明人： Choon-Beng Sia , Kiat Seng Yeo , Shao-fu Sanford Chu , Cheng Yeow Ng , Kok Wai Chew , Wang Ling Goh
IPC分类号： H01F7/06 , H01F3/00
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902 , Y10T29/4906 , Y10T29/49073 , Y10T29/49165
摘要： A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.
摘要翻译：提供了一种制造3-D螺旋堆叠电感器的方法，其具有多个电平的多个匝数的基板，其中电平的数量从电感器的内部匝数增加到外部匝数。第一连接部分和第二连接部分分别连接到内匝和最外匝，电介质材料包含基片上的第一和第二连接部分和多个匝。

8. 发明申请

US20100109097A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN 有权
标题翻译：集成电路系统采用高压排水
公开(公告)号：US20100109097A1
公开(公告)日：2010-05-06
申请号：US12262120
申请日：2008-10-30
申请人： Guowei Zhang , Yisuo Li , Ming Li , Purakh Raj Verma , Shao-fu Sanford Chu
发明人： Guowei Zhang , Yisuo Li , Ming Li , Purakh Raj Verma , Shao-fu Sanford Chu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7834
摘要： A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.
摘要翻译：一种用于制造集成电路系统的方法，包括：提供包括有源器件的衬底; 在所述衬底中形成漂移区域，所述漂移区域部分地由所述衬底的顶表面限定并与源极隔开; 并在漂移区上方形成漏极。

9. 发明授权

US07078998B2 Via/line inductor on semiconductor material 有权
标题翻译：半导体材料上的通/线电感
公开(公告)号：US07078998B2
公开(公告)日：2006-07-18
申请号：US10754973
申请日：2004-01-09
申请人： Jiong Zhang , Yi Min Wang , Shao-fu Sanford Chu
发明人： Jiong Zhang , Yi Min Wang , Shao-fu Sanford Chu
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902
摘要： A spiral inductor is provided including a substrate and an inductor dielectric layer over the substrate having a spiral opening provided therein. The spiral inductor is in the spiral opening with the spiral inductor including a plurality of parallel spiral vias connected together at center proximate and center distal ends of the spiral inductor.
摘要翻译：提供螺旋电感器，其包括衬底和在其上设置有螺旋开口的衬底上的电感器电介质层。螺旋电感器处于螺旋形开口中，螺旋电感器包括在螺旋电感器的中心近端和中心远端处连接在一起的多个平行螺旋通孔。

10. 发明授权

US07049201B2 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US07049201B2
公开(公告)日：2006-05-23
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
发明人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

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