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1. 发明申请

US20120079228A1 DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY 有权
标题翻译：数字计数器分为短暂和长时间访问时间记忆
公开(公告)号：US20120079228A1
公开(公告)日：2012-03-29
申请号：US12890479
申请日：2010-09-24
申请人： EDMUND G. CHEN , BRIAN ALLEYNE , ROBERT HATHAWAY , RANJIT J. ROZARIO , TODD D. BASSO
发明人： EDMUND G. CHEN , BRIAN ALLEYNE , ROBERT HATHAWAY , RANJIT J. ROZARIO , TODD D. BASSO
IPC分类号： G06F12/00
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定应该更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

2. 发明授权

US07349398B1 Method and apparatus for out-of-order processing of packets 有权
标题翻译：分组无序处理的方法和装置
公开(公告)号：US07349398B1
公开(公告)日：2008-03-25
申请号：US10193504
申请日：2002-07-10
申请人： John G. Favor , Edmund G. Chen , Stephan Meier
发明人： John G. Favor , Edmund G. Chen , Stephan Meier
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.
摘要翻译：描述了用于分组的无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。该方法还包括基于序列号从共享重排序缓冲器中重新分组，所述序列号相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排除。

3. 发明授权

US08295292B2 High performance hardware linked list processors 有权
标题翻译：高性能硬件链表处理器
公开(公告)号：US08295292B2
公开(公告)日：2012-10-23
申请号：US12783419
申请日：2010-05-19
申请人： Alfred Yiu-Chun Tse , Edmund G. Chen
发明人： Alfred Yiu-Chun Tse , Edmund G. Chen
IPC分类号： H04L12/28
CPC分类号： G06F17/30958 , H04L47/6205 , H04L49/3009 , H04L49/90 , H04L49/9015
摘要： In one embodiment, a reassign command is received for reassigning a first node identified by a first global identifier (GID) from a first context identified by a first context ID (CID) to a second context identified by a second CID, the first and second contexts representing first and second linked lists, respectively. A walk-the-chain (WTC) command having the first GID and the first CID is issued to a first linked list processor. The first linked list processor is configured to access one or more nodes of the first context in an attempt to dequeue the first node from the first context. An enqueue command having the first GID and the second CID is issued to a second linked list processor. The second linked list processor is configured to insert the first node to the second context. The first and second linked list processors are cascaded to form a pipeline.
摘要翻译：在一个实施例中，接收重新分配命令以将由第一全局标识符（GID）识别的第一节点从由第一上下文ID（CID）标识的第一上下文标识到由第二CID标识的第二上下文重新分配，第一和第二分别表示第一和第二链表的上下文。具有第一GID和第一CID的步行链（WTC）命令被发布到第一链表处理器。第一链表处理器被配置为访问第一上下文的一个或多个节点，以试图从第一上下文出发第一节点。具有第一GID和第二CID的入队命令被发布到第二链表处理器。第二链表处理器被配置为将第一节点插入第二上下文。第一和第二链表处理器被级联以形成流水线。

4. 发明申请

US20110286463A1 HIGH PERFORMANCE HARDWARE LINKED LIST PROCESSORS 有权
标题翻译：高性能硬件链接列表处理器
公开(公告)号：US20110286463A1
公开(公告)日：2011-11-24
申请号：US12783419
申请日：2010-05-19
申请人： Alfred Yiu-Chun Tse , Edmund G. Chen
发明人： Alfred Yiu-Chun Tse , Edmund G. Chen
IPC分类号： H04L12/56
CPC分类号： G06F17/30958 , H04L47/6205 , H04L49/3009 , H04L49/90 , H04L49/9015
摘要： In one embodiment, a reassign command is received for reassigning a first node identified by a first global identifier (GID) from a first context identified by a first context ID (CID) to a second context identified by a second CID, the first and second contexts representing first and second linked lists, respectively. A walk-the-chain (WTC) command having the first GID and the first CID is issued to a first linked list processor. The first linked list processor is configured to access one or more nodes of the first context in an attempt to dequeue the first node from the first context. An enqueue command having the first GID and the second CID is issued to a second linked list processor. The second linked list processor is configured to insert the first node to the second context. The first and second linked list processors are cascaded to form a pipeline.
摘要翻译：在一个实施例中，接收重新分配命令以将由第一全局标识符（GID）标识的第一节点从由第一上下文ID（CID）标识的第一上下文标识到由第二CID标识的第二上下文重新分配，第一和第二分别表示第一和第二链表的上下文。将具有第一GID和第一CID的步行链（WTC）命令发布到第一链表处理器。第一链表处理器被配置为访问第一上下文的一个或多个节点，以试图从第一上下文出发第一节点。具有第一GID和第二CID的入队命令被发布到第二链表处理器。第二链表处理器被配置为将第一节点插入第二上下文。第一和第二链表处理器被级联以形成流水线。

5. 发明授权

US07852846B2 Method and apparatus for out-of-order processing of packets 有权
标题翻译：分组无序处理的方法和装置
公开(公告)号：US07852846B2
公开(公告)日：2010-12-14
申请号：US12054236
申请日：2008-03-24
申请人： John G. Favor , Edmund G. Chen , Stephan Meier
发明人： John G. Favor , Edmund G. Chen , Stephan Meier
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.
摘要翻译：描述了用于分组的无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。该方法还包括基于序列号从共享重排序缓冲器中重新分组，所述序列号相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排除。

6. 发明授权

US07512129B1 Method and apparatus for implementing a switching unit including a bypass path 有权
标题翻译：用于实现包括旁路路径的切换单元的方法和装置
公开(公告)号：US07512129B1
公开(公告)日：2009-03-31
申请号：US10299236
申请日：2002-11-18
申请人： John G. Favor , Edmund G. Chen , Ruchi Wadhawan
发明人： John G. Favor , Edmund G. Chen , Ruchi Wadhawan
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： H04L49/9094 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9047
摘要： A method and apparatus for processing out-of-order processing of packets is described. In one embodiment, the method includes receiving a packet, which is in an original position relative to other packets; and attempting, by a primary processing unit, to classify and process the packet. The method also includes determining whether the packet was completely classified and processed by the primary processing unit; and upon determining that the primary processing unit completely classified and processed the packet, bypassing a secondary processing unit. The method also includes transmitting the packet onto a network, the packet being transmitted in its original position relative to the other packets.
摘要翻译：描述了用于处理分组的无序处理的方法和装置。在一个实施例中，该方法包括接收相对于其他分组处于原始位置的分组; 并且由主处理单元尝试对分组进行分类和处理。该方法还包括确定分组是否被主处理单元完全分类和处理; 并且一旦确定所述主处理单元完全对所述分组进行了分类和处理，则绕过所述辅助处理单元。该方法还包括将分组发送到网络上，该分组相对于其他分组在其原始位置被发送。

7. 发明申请

US20080259928A1 Method and Apparatus for Out-of-Order Processing of Packets using Linked Lists 有权
标题翻译：使用链接列表对包进行无序处理的方法和装置
公开(公告)号：US20080259928A1
公开(公告)日：2008-10-23
申请号：US12054235
申请日：2008-03-24
申请人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
发明人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
IPC分类号： H04L12/56
CPC分类号： H04L49/9094 , H04L49/90
摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.
摘要翻译：将参照具体实施方式和附图更好地描述本发明的这些和其它方面。描述了使用链表对包进行无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于全球秩序。该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

8. 发明授权

US07206310B1 Method and apparatus for replicating packet data with a network element 有权
标题翻译：用网络元件复制分组数据的方法和装置
公开(公告)号：US07206310B1
公开(公告)日：2007-04-17
申请号：US10032729
申请日：2001-12-28
申请人： Edmund G. Chen , Ranjit Rozario , Ravikrishna Cherukuri
发明人： Edmund G. Chen , Ranjit Rozario , Ravikrishna Cherukuri
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： H04L49/201 , H04L49/103
摘要： A method and apparatus for replicating packet data within a network element are described herein. In one embodiment, a method includes storing packet data within a storage element, maintaining a transmit count value of the storage element, determining a release count value of the storage element, comparing the transmit count value and the release count value, and de-allocating the storage element in response to comparing the transmit count value and the release count value.
摘要翻译：本文描述了用于在网络元件内复制分组数据的方法和装置。在一个实施例中，一种方法包括将分组数据存储在存储元件内，维持存储元件的发送计数值，确定存储元件的释放计数值，比较发送计数值和释放计数值，以及解除分配存储元件响应于比较发送计数值和释放计数值。

9. 发明授权

US07349399B1 Method and apparatus for out-of-order processing of packets using linked lists 有权
标题翻译：使用链表对数据包进行无序处理的方法和装置
公开(公告)号：US07349399B1
公开(公告)日：2008-03-25
申请号：US10327555
申请日：2002-12-20
申请人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
发明人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.
摘要翻译：将参照具体实施方式和附图更好地描述本发明的这些和其它方面。描述了使用链表对包进行无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于全球秩序。该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

10. 发明授权

US08700874B2 Digital counter segmented into short and long access time memory 有权
标题翻译：数字计数器分为短和长访问时间存储器
公开(公告)号：US08700874B2
公开(公告)日：2014-04-15
申请号：US12890479
申请日：2010-09-24
申请人： Edmund G. Chen , Brian Alleyne , Robert Hathaway , Ranjit J. Rozario , Todd D. Basso
发明人： Edmund G. Chen , Brian Alleyne , Robert Hathaway , Ranjit J. Rozario , Todd D. Basso
IPC分类号： G06F12/00
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定应该更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

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